SoIC Package Sidewall Glue Layer for Dielectric Adhesion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing complex integrated circuit packages, such as increased instability and stress between semiconductor dies, leading to higher failure rates and manufacturing costs, particularly in System on Integrated Chip (SoIC) and 3D integrated circuit (3DIC) technologies.
Innovation Solution
A method involving the deposition of a nitrogen-containing glue layer, such as silicon nitride, on semiconductor dies before filling with a dielectric material, which enhances adhesion and step coverage, thereby improving the bonding process and reducing the risk of die loss during subsequent fabrication steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If device dies are stacked using 3DIC solutions to reduce footprint, then manufacturing cost is saved and device performance is optimized, but instability and stress in materials between semiconductor dies increase failure rate and manufacturing cost
Solution Approach 1:
The patent introduces an intermediary material layer between stacked semiconductor dies to improve bonding and reduce stress. This intermediary layer acts as a mediator that enhances the interface between dies, preventing direct contact that causes instability and stress concentration, thereby resolving the reliability issue while maintaining the compact 3DIC architecture.
Solution Approach 2:
The patent employs composite material structures in the bonding interfaces between semiconductor dies. By using composite materials with tailored properties, the solution addresses both the mechanical stress and thermal expansion mismatches that arise in stacked configurations, improving reliability without sacrificing the footprint reduction benefits of 3DIC stacking.
2Productivity
If more device dies are packaged in the same package to achieve more functions, then integration density increases, but material instability and stress between dies increase failure rate
Solution Approach 1:
The patent divides the package into segmented regions with intermediate bonding layers between each die. This segmentation approach allows stress management and material stability improvement at each interface, enabling higher integration density while maintaining reliability by treating each die interface as a separate, optimized unit rather than a continuous stress path.
3Shape
If dielectric filling material is deposited between semiconductor dies, then gaps are filled and planarization is achieved, but adhesion between dies and filling material may be insufficient causing die loss
Solution Approach 1:
The patent applies preliminary surface treatment or adhesion-promoting layers to the semiconductor die surfaces before depositing the dielectric filling material. This preliminary action ensures that when the dielectric material is subsequently deposited to achieve planarization, strong adhesion is already established, preventing die loss during or after the planarization process.
4Ease of manufacture
If conventional packaging processes are used without additional glue layers, then manufacturing steps are simpler, but adhesion between semiconductor dies and dielectric filling material is poor leading to die loss and arcing
Solution Approach 1:
The patent introduces a glue layer as an intermediary substance between the semiconductor dies and the dielectric filling material. This glue layer serves as a mediator that simultaneously improves adhesion strength and provides arc resistance, addressing the reliability issues without significantly complicating the manufacturing process, as the glue layer application can be integrated into existing deposition sequences.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The glue layer significantly improves adhesion between semiconductor dies and dielectric filling materials, reducing die loss and arcing during planarization, and enhances the overall reliability and efficiency of the packaging process.
Implementation Method 1
a sidewall portion of a glue layer is formed on the sidewall of the first semiconductor die
Implementation Method 2
a second angle is formed between the sidewall portion of the glue layer and the top surface of the carrier wafer, and the second angle is greater than the first angle
Data Source
AI summary
The present disclosure relates to a method for fabricating a system on integrated chip (SoIC) package. Particularly, a glue layer is deposited on sidewalls of semiconductor dies prior to depositing a dielectric filling material between the semiconductor dies. The glue layer may be a nitrogen containing layer, such as silicon nitride, silicon carbon nitride, and silicon oxygen nitride. The dielectric filling material may be a silicon oxide formed from TEOS or mDEOS. The glue layer increases adhesion between the dielectric filling material and semiconductor dies.