SoIC Die Stack Layout Checks for Delamination-Resistant Bonding

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Solution Overview

Problem

SoIC die stacks bonded using hybrid or fusion bonding are prone to chip delamination due to weaker bonding forces, leading to open circuits or defective structures when subjected to external impacts, necessitating a design rule check to prevent such failures.

Innovation Solution

Implementing a design rule check that sets specific lateral distances between the SoIC die stack and neighboring components or edges to prevent collisions and ensure secure bonding, using thresholds to determine if the SoIC die stack passes or fails the design rule check, thereby preventing chip delamination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If SoIC die stacks are bonded using hybrid or fusion bonding to achieve high integration density, then integration density and system performance are improved, but bonding strength is reduced making the structure prone to delamination under external impacts

Engineering Contradiction:

Improveintegration densityVSAvoidbonding strength

Core Design Contradiction:

Quantity of substanceVSStrength

Solution Approach 1:

The patent implements design rule checks and spacing requirements before the bonding process to prevent delamination issues. By pre-establishing adequate lateral distances between die stacks and neighboring components, the design anticipates and prevents bonding failures under external impacts before they occur in production.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces protective spacing zones around die stacks as a cushioning measure. These lateral distance buffers act as a protective margin that absorbs mechanical stress and prevents direct contact between die stacks and neighboring components, reducing the risk of delamination when external impacts occur.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

2Reliability

If lateral spacing between die stacks and neighboring components is increased to prevent delamination, then bonding reliability is improved, but package area is reduced

Engineering Contradiction:

Improvebonding reliabilityVSAvoidpackage area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent establishes specific parameter thresholds for lateral distances between die stacks and neighboring components. By defining minimum spacing parameters in design rules, the patent optimizes the balance between reliability (preventing delamination) and area utilization, ensuring adequate protection without excessive waste of package space.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20240413110A1Method for fabricating semiconductor package including SOIC die stacks

Publication Date: 2024.12.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method includes the following steps: providing a first base structure; bonding a plurality of chips to a top surface of the first base structure; bonding two or more dies together using fusion bonding or hybrid bonding to form a die stack; and bonding the die stack to the top surface of the first base structure. A first lateral distance, in a first direction, between a first boundary of the die stack and a boundary of a neighboring chip among the plurality of chips is larger than a first threshold distance.