SoIS Fan-Out Interconnect Structure for High-Density Routing
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturizing integrated circuits while maintaining high functionality and performance, particularly in achieving efficient electrical routing and connection density within small packages, which is crucial for applications requiring high-speed operations and reduced package size.
Innovation Solution
The development of a semiconductor device manufacturing method involving the formation of a redistribution layer over a carrier substrate, followed by the attachment of interconnect devices and through-molding vias, which are embedded in a molding compound, and further interconnected with additional redistribution layers to create a high-density electrical routing system, allowing for efficient signal transmission and reduced package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of input/output pads is increased to achieve high functionality, then the functional density is improved, but the package size increases
Solution Approach 1:
The patent implements fan-out wiring that extends electrical connections from the chip surface to the package underside, utilizing the third dimension (vertical depth) to route signals. This allows contact pads to be positioned at the chip edge while electrical connections are made at the package bottom, effectively adding a dimensional aspect to the interconnection architecture that increases functional density without proportionally increasing package footprint.
Solution Approach 2:
The patent introduces an intermediary structure consisting of the fan-out wiring layer and molding compound that mediates between the chip contact pads and the external package contacts. This intermediary system allows electrical signals to be routed from the chip surface through the package substrate to external contacts, enabling high functionality while maintaining compact package dimensions by distributing connections across multiple layers and locations.
2Quantity of substance
If the minimum feature size is reduced to increase integration density, then more components can be integrated, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the interconnection system into distinct functional layers: chip contact pads, fan-out wiring layers, molding compound, and package substrate contacts. This segmentation allows each layer to be optimized independently for its specific function, with the fan-out wiring providing robust interconnection structures that are less sensitive to minimum feature size variations, thereby enabling high integration density while maintaining manufacturability.
Solution Approach 2:
The fan-out wiring architecture transitions from two-dimensional planar interconnections on the chip surface to three-dimensional routing that extends vertically through the package substrate. This dimensional transition allows signals to be routed through additional space, reducing the demand for ultra-fine feature sizes in the planar direction and enabling higher integration density with relaxed manufacturing precision requirements.
3Length of moving object
If fan-out wiring is implemented to achieve larger pitch for electrical contacts, then contact pitch is improved, but device complexity increases
Solution Approach 1:
The fan-out wiring layer serves multiple functions simultaneously: it provides electrical interconnection between chip pads and package contacts, acts as a structural support framework, enables larger contact pitch, and facilitates heat dissipation pathways. This multi-functionality reduces the need for separate dedicated structures for each function, thereby managing device complexity while achieving improved contact pitch.
Solution Approach 2:
The patent merges the electrical interconnection function with the package substrate structure by integrating the fan-out wiring directly into the molding compound and package substrate assembly. This consolidation combines what could be separate components (wiring layer, substrate, encapsulation) into an integrated structure, reducing overall device complexity while enabling larger contact pitch through the fan-out architecture.
Data Source
AI summary
Semiconductor devices and methods of forming the semiconductor devices are described herein that are directed towards the formation of a system on integrated substrate (SoIS) package. The SoIS package includes an integrated fan out structure and a device redistribution structure for external connection to a plurality of semiconductor devices. The integrated fan out structure includes a plurality of local interconnect devices that electrically couple two of the semiconductor devices together. In some cases, the local interconnect device may be a silicon bus, a local silicon interconnect, an integrated passive device, an integrated voltage regulator, or the like. The integrated fan out structure may be fabricated in wafer or panel form and then singulated into multiple integrated fan out structures. The SoIS package may also include an interposer connected to the integrated fan out structure for external connection to the SoIS package.