Solar Cell Intrinsic Layer Formation via Catalytic CVD
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Solution Overview
Problem
Conventional solar cell manufacturing methods face challenges in preventing dopant gases from adhering to the substrate's surface during the formation of intrinsic semiconductor layers, leading to impurities at the interface and reduced conversion efficiency.
Innovation Solution
The method involves forming intrinsic semiconductor layers on both principle planes of a crystalline semiconductor substrate using catalytic chemical vapor deposition, with catalyzers positioned to decompose raw gases, ensuring that dopant gases do not contaminate the interface between the substrate and the semiconductor layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If plasma CVD is used to form semiconductor layers on both principle planes of the substrate, then the solar cell structure is completed, but dopant gases adhere to the substrate surface and contaminate the interface between the substrate and intrinsic semiconductor layer
Solution Approach 1:
The patent applies preliminary action by forming the intrinsic semiconductor layer on both principle planes of the substrate before forming the doped semiconductor layers. This sequence prevents dopant gases from contaminating the substrate-intrinsic semiconductor layer interface, as the intrinsic layer acts as a barrier during subsequent doped layer formation processes.
Solution Approach 2:
The patent inverts the conventional manufacturing sequence by forming intrinsic semiconductor layers first on both principle planes, then forming doped semiconductor layers on top. This reversal of the normal process order (where doped layers are typically formed first) prevents dopant contamination of the substrate interface while maintaining manufacturing efficiency.
2Adaptability or versatility
If the substrate is conveyed between multiple reaction chambers to form different semiconductor layers, then all necessary layers are formed, but the process becomes complex and time-consuming
Solution Approach 1:
The patent merges the formation of intrinsic semiconductor layers on both principle planes into a single process step performed before doped layer formation. By combining these operations and establishing a fixed sequence (intrinsic layers first, then doped layers), the patent reduces the need for multiple conveyances and complex chamber switching, thereby simplifying the overall manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the interfacial quality and photoelectric conversion efficiency of the solar cell by preventing dopant impurities from entering the boundary faces, resulting in a more efficient solar cell manufacturing process.
Implementation Method 1
forming intrinsic semiconductor layers on both principle planes of a substrate made of a semiconductor material by catalytic chemical vapor deposition
Implementation Method 2
catalyzers which heat up by receiving an electric current and decompose raw gases
Data Source
AI summary
The present invention is a solar cell 500 comprising the substrate 510 made of a crystalline semiconductor, an i-type semiconductor layer 520a and an i-type semiconductor layer 520b each made of an amorphous semiconductor, and a first-conductivity type semiconductor layer 530 and a second-conductivity type semiconductor layer 540 each made of an amorphous semiconductor, in which by catalytic chemical vapor deposition in which catalyzers decompose raw gas when being heated by receiving an electric current, the i-type semiconductor layer 520a is formed on the principle plane 515a by the catalyzer placed at the position facing the principle plane 515a, the i-type semiconductor layer 520b is formed on the principle plane 515b by the catalyzer placed at the position facing the principle plane 515b are formed on the i-type semiconductor layer 520a and the i-type semiconductor layer 520b on the substrate 510.