Solar Cell Isolation Layout Without Reactive Ion Etching
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Solution Overview
Problem
Current solar cell manufacturing methods using reactive ion etching (RIE) for forming isolation structures between n-type and p-type conductive regions lead to contamination of semiconductor equipment, increased manufacturing costs, and higher defective rates due to incomplete isolation on edge substrates.
Innovation Solution
A solar cell manufacturing method that involves forming a polycrystalline silicon layer, texturing the front surface, diffusing dopants, and using a passivation layer to create naturally spaced conductive regions without reactive ion etching, thereby simplifying the process and reducing equipment contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If reactive ion etching (RIE) is used to form isolation structures, then isolation between conductive regions is achieved, but equipment contamination and manufacturing cost increase
Solution Approach 1:
The patent extracts and removes the harmful byproducts (SF6, Cl2, O2 gases) generated during the RIE process through a dedicated exhaust system. The exhaust nozzle is positioned to directly remove contaminated gases from the etching zone, preventing them from contaminating the equipment and substrates during transfer operations.
Solution Approach 2:
The patent introduces an intermediary exhaust system between the RIE chamber and the external environment. This intermediary system captures and removes harmful gases before they can contaminate equipment, acting as a mediator that protects the manufacturing environment from the harmful effects of the etching process.
2Manufacturing precision
If RIE is used for isolation formation, then conductive regions are isolated, but additional auxiliary devices are required increasing manufacturing cost
Solution Approach 1:
The patent merges the exhaust function with the existing RIE chamber structure by integrating an exhaust nozzle into the chamber. This combination eliminates the need for separate auxiliary devices for gas removal, reducing system complexity while maintaining effective isolation formation capabilities.
3Productivity
If multiple substrates are arranged in a tray for RIE processing, then throughput is improved, but isolation uniformity deteriorates on edge substrates
Solution Approach 1:
The patent applies local quality by positioning the exhaust nozzle to create a localized exhaust flow pattern that specifically addresses the needs of edge substrates in the tray. The exhaust flow is directed to ensure uniform byproduct removal across all substrate positions, including edges, maintaining consistent isolation quality throughout the batch.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively forms stable isolation structures between conductive regions, reduces equipment contamination, and lowers manufacturing costs by eliminating the need for additional auxiliary devices and improving the uniformity of the isolation process.
Implementation Method 1
a front surface texturing operation of removing the polycrystalline silicon layer formed on a front surface of the semiconductor substrate and texturing the front surface of the semiconductor substrate
Implementation Method 2
a second conductive region forming operation of diffusing a second dopant on the front surface of the semiconductor substrate to form a second conductive region
Data Source
AI summary
Discussed is a solar cell including a single crystalline silicon substrate, a polycrystalline silicon layer on a back surface and side surfaces of the single crystalline silicon substrate, a diffusion region on a front surface of the single crystalline silicon substrate, a front passivation layer on the diffusion region, a back passivation layer on the polycrystalline silicon layer, a first electrode connected to the diffusion region through the front passivation layer, and a second electrode connected to the polycrystalline silicon layer through the back passivation layer, wherein the side surfaces of the single crystalline silicon substrate includes a first portion without the polycrystalline silicon layer and a second portion with the polycrystalline silicon layer.