Solar Cell Passivation via Low-Temperature Silicon Oxide
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Solution Overview
Problem
Conventional high-temperature processes for forming silicon oxide layers in solar cells result in increased interface trap density, degraded chemical passivation characteristics, and reduced bulk lifetime, making it difficult to manufacture efficient solar cells with shallow emitter regions and high carrier collection efficiency.
Innovation Solution
A method involving the formation of silicon oxide layers with a thickness of 1 nm to 3 nm at a low temperature, using an aluminum oxide layer in either the front or back passivation part, and a hydrogenated silicon nitride layer, which improves passivation characteristics and reduces recombination velocity at the semiconductor surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high-temperature processes are used to form silicon oxide layers, then the silicon oxide layer formation is achieved, but interface trap density increases and chemical passivation characteristics are degraded
Solution Approach 1:
The patent changes the temperature parameter from conventional high-temperature processes to low-temperature processes (below 450°C) for forming silicon oxide layers. This parameter change enables the formation of high-quality silicon oxide layers with low interface trap density while avoiding the degradation of chemical passivation characteristics that occurs with high-temperature processing.
Solution Approach 2:
The patent employs a composite passivation structure consisting of multiple layers including silicon oxide layers, aluminum oxide layers, and hydrogenated silicon nitride layers. This composite material approach allows each layer to contribute specific properties: silicon oxide provides chemical passivation, aluminum oxide provides field effect passivation, and hydrogenated silicon nitride provides additional passivation and protection, achieving superior overall passivation performance.
2Manufacturing precision
If high-temperature processes are used to form silicon oxide layers, then the silicon oxide layer formation is achieved, but bulk lifetime is reduced
Solution Approach 1:
The patent changes the processing temperature parameter to low-temperature conditions (below 450°C), which prevents the thermal damage and impurity activation that occur during high-temperature processing. This parameter change preserves bulk lifetime by avoiding the creation of bulk defects and the activation of metallic impurities that would otherwise reduce carrier lifetime.
3Productivity
If shallow emitter regions are manufactured, then carrier collection efficiency is improved, but it becomes difficult to manufacture with conventional high-temperature processes
Solution Approach 1:
The patent changes the temperature parameter to low-temperature processing, which enables the formation of shallow emitter regions without the thermal diffusion that occurs in high-temperature processes. This allows precise control of emitter depth and profile, achieving shallow emitter structures that improve carrier collection efficiency while being manufacturable with the low-temperature process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the chemical passivation and field effect passivation of solar cells, allowing for improved efficiency and long-term reliability by maintaining low interface trap density and preventing bulk lifetime reduction.
Implementation Method 1
enhances the chemical passivation and field effect passivation of solar cells
Implementation Method 2
enhances the chemical passivation and field effect passivation of solar cells
Implementation Method 3
A method involving the formation of silicon oxide layers with a thickness of 1 nm to 3 nm at a low temperature
Data Source
AI summary
A solar cell is discussed. The solar cell includes a semiconductor substrate of a first conductive type, an emitter region of a second conductive type opposite the first conductive type, which is positioned at a front surface of the semiconductor substrate, a front passivation part positioned on a front surface of the emitter region, a front electrode part which passes through the front passivation part and is electrically connected to the emitter region, a back passivation part positioned on a back surface of the semiconductor substrate, and a back electrode part which passes through the back passivation part and is electrically connected to the semiconductor substrate. The front passivation part and the back passivation part each include a silicon oxide layer. One of the front passivation part and the back passivation part includes an aluminum oxide layer.


