Solar Cell Passivation Layer Thickness Control
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Solution Overview
Problem
In tunneling solar cells, the high-temperature annealing process used to improve passivation quality of the silicon oxide layer leads to excessive growth, compromising carrier transport and reducing the passivation capability, which in turn limits the open-circuit voltage due to the close band gaps of polysilicon and single-crystal silicon.
Innovation Solution
A solar cell structure is developed with a silicon substrate, a passivation layer, a doped polysilicon layer, and a semiconductor layer with a greater band gap than the substrate, where holes in the doped polysilicon and passivation layers expose the substrate surface, allowing effective passivation and improving open-circuit voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature annealing process is performed to improve passivation quality of silicon oxide layer, then passivation quality is improved, but silicon oxide layer thickness exceeds 2 nm which compromises carrier transport
Solution Approach 1:
A doped amorphous silicon layer is formed on the silicon oxide layer before annealing to prevent excessive growth. This preliminary protective layer ensures that during high-temperature annealing, the silicon oxide layer does not grow beyond 2 nm thickness, thereby maintaining both passivation quality and carrier transport capability.
Solution Approach 2:
The patent changes the material parameter from pure silicon oxide to a composite structure of silicon oxide with doped amorphous silicon layer. This parameter change allows the system to achieve good passivation characteristics without requiring thick silicon oxide growth, thus resolving the contradiction between passivation quality and carrier transport.
2Manufacturing precision
If doped amorphous silicon layer is formed to prevent excessive growth, then thickness control is improved, but during annealing holes are generated which reduces passivation capability
Solution Approach 1:
The doped amorphous silicon layer acts as an intermediary between the silicon oxide layer and the external environment. During annealing, it transforms into doped polysilicon which serves as a mediator to prevent direct interaction that would generate holes, thereby maintaining passivation capability while controlling thickness.
Solution Approach 2:
The patent uses a composite material structure combining silicon oxide layer and doped amorphous silicon layer (which transforms to doped polysilicon). This composite structure provides both thickness control and maintains passivation capability by preventing hole generation during annealing.
3Ease of manufacture
If polysilicon layer is used, then manufacturing is simplified, but band gap is close to 1.1 eV which cannot effectively passivate surface defects
Solution Approach 1:
The patent applies local quality by using doped polysilicon specifically at the interface region where it is needed for field effect passivation, while maintaining a separate silicon oxide layer for primary passivation. This localized application of polysilicon provides the necessary electrical field to passivate surface defects without requiring the entire structure to have polysilicon properties.
Solution Approach 2:
The patent changes the doping concentration parameter of the polysilicon layer to create a high-density doping state that generates a strong field effect. This parameter change allows the polysilicon layer to effectively passivate surface defects through electrical field effects rather than relying on material band gap properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure effectively increases the open-circuit voltage of the solar cell by preventing excessive passivation layer growth and enhancing carrier transport, resulting in improved solar cell performance.
Implementation Method 1
the band gap of the semiconductor layer is greater than the band gap of the silicon substrate
Implementation Method 2
the carriers in the silicon wafer cannot be freely transported via the tunneling mechanism
Implementation Method 3
during the annealing process, the doped amorphous silicon layer is changed into a doped polysilicon layer
Data Source
AI summary
A solar cell is provided. The solar cell includes a Si substrate having a first surface and a second surface opposite to each other, an emitter, a first electrode, a doped region, a passivation layer, a doped polysilicon layer, a semiconductor layer, and a second electrode. The emitter is disposed on the first surface. The first electrode is disposed on the emitter. The doped region is disposed in the second surface. The passivation layer is disposed on the second surface. The doped polysilicon layer is disposed on the passivation layer, wherein a plurality of holes penetrates the doped polysilicon layer and the passivation layer and exposes a portion of the second surface. The semiconductor layer is disposed on the doped polysilicon layer and in the holes. The band gap of the semiconductor layer is greater than that of the Si substrate. The second electrode is disposed on the semiconductor layer.