Solar Cell Emitter Segmentation for Reduced Power Losses
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current solar cell manufacturing techniques face challenges in increasing efficiency and cost-effectiveness, particularly in the fabrication of solar cell emitter regions with differentiated P-type and N-type architectures, which affect the overall performance and power generation of solar cells.
Innovation Solution
The implementation of novel methods for fabricating solar cells with differentiated P-type and N-type emitter regions, including the use of polycrystalline silicon emitter regions and silicide formation, which simplifies the metallization process and reduces alignment issues, and the incorporation of a self-aligned silicide process for contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional solar cell manufacturing techniques are used, then the fabrication process is established and reliable, but efficiency and cost-effectiveness are limited
Solution Approach 1:
The solar cell emitter regions are segmented into differentiated P-type and N-type regions with distinct architectures. The P-type regions have one configuration while the N-type regions have another, allowing each to be optimized independently for its specific function, thereby reducing power losses and improving overall manufacturing efficiency
Solution Approach 2:
Different local architectures are implemented for P-type and N-type emitter regions based on their specific requirements. The P-type regions use one structural configuration optimized for hole collection while N-type regions use another configuration optimized for electron collection, achieving local optimization that reduces energy losses
2Reliability
If complex metallization processes are used, then contact formation can be achieved, but alignment issues and fabrication complexity increase
Solution Approach 1:
The metallization process is merged with the emitter region fabrication process. The same doping and deposition steps that create the P-type and N-type emitter regions also form the metallization contacts, eliminating separate alignment steps and reducing fabrication complexity while maintaining reliable contact formation
Solution Approach 2:
The emitter region structures self-align to provide the metallization contact patterns. The differentiated P-type and N-type region architectures automatically define the contact locations and geometries, eliminating the need for separate photolithography and alignment steps for metallization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances solar cell efficiency by reducing power losses and simplifying the fabrication process, leading to improved power generation and cost-effectiveness.
Implementation Method 1
Photovoltaic cells, commonly known as solar cells, are well known devices for direct conversion of solar radiation into electrical energy
Implementation Method 2
Solar radiation impinging on the surface of, and entering into, the substrate creates electron and hole pairs in the bulk of the substrate. The electron and hole pairs migrate to p-doped and n-doped regions in the substrate, thereby generating a voltage differential between the doped regions
Data Source
AI summary
Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region.