Solder Array Thermal Interfaces for Multi-Chip Die Height Variation
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Solution Overview
Problem
Warpage and thermal performance issues in thin integrated circuit (IC) device packages due to differences in temperature coefficients of thermal expansion (CTE) between device and package materials, and the gradual pump-out of thermal interface material (TIM) as the die cycles between cold and hot phases.
Innovation Solution
Fabrication of solderable thermal interface structures on IC dies and heat spreaders, with a solder array thermal interconnects, to address warpage and thermal performance issues by providing discrete interfaces for thermal interconnects and accommodating varying IC die thicknesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If thermal interface material (TIM) is used to accommodate step height variation between neighboring IC dies, then manufacturing flexibility is improved, but TIM thickness increases resulting in higher thermal resistance
Solution Approach 1:
The thermal interface structure is segmented into discrete solder array interconnects rather than a continuous TIM layer. Each solder interconnect independently bridges the gap between heat spreader and IC die, eliminating the need for thick TIM while maintaining adaptability to step height variations through selective solder placement on varying die surfaces.
Solution Approach 2:
The invention changes the physical state and distribution of the thermal interface material from a continuous thick layer to discrete solder interconnects with controlled height and position. This parameter change allows the thermal path to adapt to varying die thicknesses while maintaining optimal thermal contact without excessive TIM thickness.
2Volume of moving object
If thin form-factor packages are used to reduce device size, then device compactness is improved, but TIM pump-out occurs due to die surface curvature changes during thermal cycling
Solution Approach 1:
The continuous TIM layer is replaced with discrete solder array interconnects that are less susceptible to pump-out effects. The segmented structure allows each solder joint to independently maintain its thermal interface, preventing the gradual loss of thermal contact that occurs with continuous TIM layers under thermal cycling and die curvature changes.
Solution Approach 2:
The solder array interconnects are designed as robust, replaceable thermal pathways that can withstand thermal cycling without degradation. Unlike TIM that gradually pumps out and loses effectiveness, the solder joints maintain their integrity throughout the device lifetime, providing reliable thermal contact in thin form-factor packages.
3Reliability
If discrete solder array thermal interconnects are implemented to reduce thermal resistance, then thermal performance is improved, but manufacturing complexity increases
Solution Approach 1:
The solder array thermal interconnects are merged with the existing electrical interconnect structure, using the same solder bump fabrication processes and alignment methodologies. This integration allows the thermal and electrical pathways to be created simultaneously during standard IC packaging operations, reducing manufacturing complexity despite the discrete nature of the thermal interconnects.
Solution Approach 2:
The solder array serves dual functions as both electrical interconnects and thermal pathways. This multi-functionality eliminates the need for separate thermal interface components and processes, allowing the same manufacturing operations that create electrical connections to also establish optimal thermal contact between the heat spreader and IC die.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces thermal resistance and minimizes TIM pump-out, enhancing the thermal performance and reliability of IC device packages, even in multi-chip assemblies with varying die thicknesses.
Implementation Method 1
a plurality of solder array thermal interconnects coupled to the plurality of thermal interface structures... effectively reduces thermal resistance
Implementation Method 2
Temperature coefficients of thermal expansion (CTE) may differ between a device and package materials, which may contribute to the problem of warpage
Data Source
AI summary
Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.