Solder Bump Height Equalization After Reflow in IC Packaging
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Solution Overview
Problem
The challenge in integrated circuit packaging is achieving uniform bump heights after reflow, as existing dual litho processes struggle to fabricate multiple different bump heights efficiently, leading to variations that can disrupt proper connection with semiconductor dies or other components.
Innovation Solution
A method using a first dry film resist patterned with openings for critical dimensions, followed by selective inkjet deposition of resist material to cover plated bumps, allowing for additional solder deposition only on uncovered bumps, ensuring all bumps reach a substantially even height after reflow without the need for multiple litho loops, thus controlling bump heights across various sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dual litho processes are used to fabricate multiple different bump heights, then bump height variation can be controlled, but manufacturing complexity and process time increase significantly
Solution Approach 1:
The patent segments the litho process into two distinct stages: a first litho process that defines critical dimensions for all bumps, and a second litho process that selectively defines heights for specific bumps. This segmentation allows independent optimization of each process stage, achieving precise height control without requiring complex multi-loop lithography sequences.
Solution Approach 2:
The first litho process performs preliminary action by establishing the critical dimensions and base structure for all bumps before the second litho process selectively modifies specific bumps to achieve final height variations. This preliminary structuring simplifies the subsequent selective modification process.
2Manufacturing precision
If multiple litho loops are implemented to achieve different bump heights, then height control improves, but manufacturing time and productivity decrease
Solution Approach 1:
By dividing the litho operations into two independent, non-iterative processes, the patent eliminates the need for multiple repeated litho loops. The first process establishes base dimensions for all bumps, while the second process selectively adjusts specific bumps, achieving height differentiation in a single pass rather than through iterative loops.
Solution Approach 2:
The first litho process performs preliminary dimensioning for all bumps, establishing a foundation that reduces the complexity of subsequent selective height adjustments. This preliminary structuring allows the second process to focus only on selective modification, improving overall manufacturing efficiency.
3Manufacturing precision
If selective solder deposition is performed on uncovered bumps, then uniform bump heights are achieved, but process complexity increases
Solution Approach 1:
The patent applies local quality by using the second litho process to selectively expose only specific bumps that require additional solder deposition. This localized approach allows precise control of solder application to specific areas, achieving uniform final heights across all bumps while maintaining process simplicity through targeted rather than universal treatment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of any number of different sized bumps to achieve uniform heights post-reflow, enhancing packaging processes by maintaining coplanarity and reducing manufacturing complexity and costs.
Implementation Method 1
followed by selective inkjet deposition of resist material to cover plated bumps
Implementation Method 2
depositing, via a second plating process, a second layer of solder onto the substrate
Data Source
AI summary
Systems, apparatus, articles of manufacture, and methods to reduce variation in height of bumps after flow are disclosed. An example apparatus includes a substrate of an integrated circuit package, a first bump on the substrate, a second bump on the substrate, and a third bump on the substrate. The first bump includes first solder on a first metal pad. The first metal pad has a first width and a first thickness. The second bump includes second solder on a second metal pad. The second metal pad has a second width and a second thickness. The second width is less than the first width. The second thickness matches the first thickness. The third bump includes third solder on a third metal pad. The third metal pad has a third width. The third width less than the second width.