Solder Bump LED Package Wafer-Level Planarization
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Solution Overview
Problem
Conventional chip-scale semiconductor LED packaging methods are costly and complex, leading to reduced die yields and increased production costs due to the need for plating processes and complex manufacturing steps.
Innovation Solution
A semiconductor LED package with solder bumps formed on the chip surface during the wafer process, where the solder bumps protrude and are planarized, allowing for a resin layer to cover the chip except for the bump ends, simplifying the manufacturing process and reducing costs by eliminating the need for additional solder application and grinding steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional chip-scale LED packaging methods are used with plating processes, then solder attachment is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
Solder bumps are formed on the LED chip electrodes during the wafer fabrication process before chip separation, eliminating the need for subsequent solder application steps. This preliminary formation of solder connections simplifies the overall manufacturing process while ensuring reliable electrical and mechanical attachment.
Solution Approach 2:
The solder bump formation process is merged with the wafer fabrication process, combining multiple manufacturing steps into a single integrated process. This eliminates separate plating and solder application steps, reducing manufacturing complexity while maintaining attachment reliability.
2Reliability
If conventional packaging with additional solder application steps is used, then electrical connection is established, but production cost increases
Solution Approach 1:
Solder bumps are pre-formed on the wafer during fabrication, eliminating the need for costly post-chip solder application steps. This preliminary action reduces production costs while ensuring reliable electrical connections are established before chip separation and packaging.
Solution Approach 2:
The wafer fabrication process is made multi-functional by incorporating solder bump formation into the standard fabrication sequence, allowing the same manufacturing line to produce both the LED structure and the electrical connections without additional equipment or process steps.
3Productivity
If solder bumps are formed during wafer process and planarized, then die yields increase, but surface flatness must be controlled
Solution Approach 1:
Solder bumps are formed and planarized during the wafer fabrication process before chip separation. This preliminary planarization ensures that the chip surfaces are flat and uniform, improving die yields by preventing defects during subsequent packaging and mounting operations.
Solution Approach 2:
The surface flatness parameter is controlled through planarization processes applied to the entire wafer before chip separation. By adjusting planarization parameters such as polishing pressure, speed, and abrasives, uniform flatness is achieved across all chips, improving yield while maintaining manufacturing efficiency.
Data Source
AI summary
A semiconductor light-emitting diode (LED) package is provided and includes a semiconductor LED chip having a surface on which a first electrode and a second electrode are formed; a first solder bump formed on the first electrode and a second solder bump formed on the second electrode, the first solder bump and the second solder bump protruding from the surface of the semiconductor LED chip; and a resin layer having a bottom portion that surrounds a first side surface of the first solder bump and a second side surface of the second solder bump and covers the surface of the semiconductor LED chip.