Solder Bump Stretching for Grain Orientation Control
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Solution Overview
Problem
Solder bumps in flip-chip solder joints often experience early failure due to random grain orientation, leading to solder material dissolution caused by electromigration, which is not effectively controlled by existing assembly methods.
Innovation Solution
A process involving heating and stretching solder bumps above their melting temperature, followed by controlled cooling, to align the grain orientation and form a lamellar crystal structure that reduces crack propagation and enhances thermal mechanical reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder bumps are assembled by conventional aligning and placing methods with reflow in a conveyer oven, then the assembly process is simple and efficient, but the grain orientation of the solder bump element becomes random, leading to early failure due to electromigration
Solution Approach 1:
The patent applies parameter changes by controlling the cooling rate and temperature profile during the reflow process. By maintaining the solder bump temperature above the melting point for a specific duration and then controlling the cooling rate, the patent achieves controlled grain orientation. This transforms the random grain structure into a desired orientation that resists electromigration, thereby improving reliability without complicating the manufacturing process
Solution Approach 2:
The patent utilizes phase transitions of the solder material by heating the solder bump above its melting temperature and then controlling the solidification process. The phase change from liquid to solid during controlled cooling enables the formation of desired grain orientation and lamellar crystal structure, which improves electromigration resistance while maintaining process simplicity
2Manufacturing precision
If the solder bump temperature is maintained above the melting point for a specific duration, then the grain orientation can be controlled, but the process time increases
Solution Approach 1:
The patent applies partial action by maintaining the solder bump temperature above the melting point for a specific, optimized duration rather than prolonged heating. This controlled time period is sufficient to achieve the desired grain orientation and phase transformation, avoiding excessive process time while still obtaining the precision needed for electromigration resistance
Solution Approach 2:
The patent employs periodic action through a controlled heating and cooling cycle. The temperature is raised above the melting point, held for a specific duration to achieve phase transformation and grain orientation, then cooled at a controlled rate. This periodic thermal processing achieves precise grain control within an optimized time frame
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process significantly increases the fatigue life of solder bumps by up to 4-5 times, mitigating premature electromigration failure and improving thermal mechanical reliability through controlled grain orientation and structure formation.
Implementation Method 1
heating and stretching solder bumps above their melting temperature
Implementation Method 2
form a lamellar crystal structure that reduces crack propagation and enhances thermal mechanical reliability
Implementation Method 3
followed by controlled cooling, to align the grain orientation
Data Source
AI summary
A wafer-level pulling method includes securing a top holder to a plurality of chips. The method further includes securing a bottom holder to a wafer, wherein the plurality of chips are bonded to the wafer by a plurality of solder bumps. The method further includes softening the plurality of solder bumps. The method further includes stretching the plurality of softened solder bumps, wherein stretching the plurality of softened solder bumps comprises leveling the plurality of chips using a plurality of levelling devices separated from the plurality of chips, and a first levelling device of the plurality of levelling devices has a different structure from a second levelling device of the plurality of levelling devices.