Solder Extrusion Prevention Layer for Flip Chip Voids
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Solution Overview
Problem
In flip chip semiconductor assemblies, the formation of voids between solder bumps can lead to short circuits due to the melting and extrusion of solder during the reflow process, especially as pitch decreases, causing reliability issues.
Innovation Solution
A semiconductor package design that includes a solder extrusion prevention layer with a higher melting point than the solder, such as an oxide or nitride layer, is applied to the sidewalls of solder bumps exposed by voids, preventing short circuits by maintaining the solder in place during reflow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If solder bumps are reflowed to attach the chip to the package, then the chip is securely attached to the wiring substrate, but the solder may extrude through voids and cause short circuits between adjacent bumps
Solution Approach 1:
A solder extrusion prevention layer is formed on the sidewalls of solder bumps before the reflow process. This layer acts as a barrier that prevents solder from extruding through voids during subsequent reflow, while still allowing the solder to properly attach to the wiring substrate. The prevention layer is prepared in advance to address the potential short circuit issue before it occurs.
Solution Approach 2:
The solder extrusion prevention layer serves as an intermediary structure between the solder bump and the void space. It mediates the interaction by providing a controlled interface that allows the solder to maintain its shape and prevents uncontrolled extrusion, while still permitting the necessary thermal and mechanical processes to occur during reflow.
2Productivity
If the pitch between solder bumps is decreased to accommodate more bumps on a chip, then the I/O terminal density increases, but voids between bumps become more prone to formation and short circuits
Solution Approach 1:
The solder extrusion prevention layer is formed on the sidewalls of solder bumps before chip mounting and sealing. This preliminary structure prevents solder from extruding into voids that may form during subsequent processing, enabling closer pitch between bumps without compromising reliability.
Solution Approach 2:
The prevention layer is applied selectively to the sidewalls of solder bumps, providing localized protection where voids are most likely to form. This local quality enhancement allows for reduced pitch between bumps while maintaining reliability in the critical regions where short circuits would occur.
3Reliability
If a sealing layer is formed between solder bumps to seal the chip, then the chip is protected and sealed, but voids may form between the solders creating short circuit paths
Solution Approach 1:
The solder extrusion prevention layer acts as an intermediary barrier on the sidewalls of solder bumps. It separates the solder from the void space created during sealing, preventing solder from migrating into the void and creating short circuits, while allowing the sealing layer to properly enclose and protect the chip.
Solution Approach 2:
The harmful effect of solder extrusion into voids is extracted and prevented by the prevention layer. This layer specifically addresses the harmful factor of solder migration while maintaining the beneficial sealing function, effectively removing the short circuit risk associated with void formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents short circuits and ensures reliable connections by maintaining the solder within its intended bounds, even when voids form between solder bumps, enhancing the overall reliability of the semiconductor package.
Implementation Method 1
The solder extrusion prevention layer comprises a material having a higher melting point than the solder
Data Source
AI summary
A semiconductor package includes a wiring substrate including a plurality of solder pads; a chip including a plurality of chip pads connected to the solder pads through a plurality of solders; a sealing layer configured to seal the chip and the solders, at least one void being between the solders; and a solder extrusion prevention layer on one sidewall of the solder exposed by the at least one void.