Non-Uniform Solder Joint Layout for Thermal Cycling Reliability

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As semiconductor packages increase in size and complexity, they experience deformation and stress due to coefficient of thermal expansion mismatch with printed circuit boards, leading to reduced solder joint reliability, especially under temperature cycling and drop impact conditions.

Innovation Solution

Incorporating additional solder joints of varying shapes and sizes at strategic locations on the semiconductor package, which act as mechanical supports and increase the interfacial area with bonding pads, thereby enhancing mechanical strength and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If semiconductor packages increase in size and complexity to accommodate silicon chip volume, then the package can accommodate larger chips, but the substrate becomes thinner and deformation and stress on solder joint interfaces increase due to CTE mismatch

Engineering Contradiction:
Improvesilicon chip volumeVSAvoidsolder joint reliability
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent applies local quality by varying the solder joint sizes and shapes at different locations on the substrate. Larger solder joints are positioned at corners and edges where stress concentration occurs due to CTE mismatch, while smaller joints are placed in less stressed areas. This non-uniform distribution optimizes stress management locally throughout the package structure.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the parameters of solder joints by incorporating joints of different sizes, shapes (circular, square, rectangular, triangular, or other geometries), and distributions. This parameter variation allows the solder joint array to better accommodate thermal expansion stresses while maintaining electrical connectivity, thereby improving reliability without reducing chip volume.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If additional solder joints of varying shapes and sizes are incorporated at strategic locations, then solder joint reliability improves by increasing interfacial area and cracking path length, but device complexity increases

Engineering Contradiction:
Improvesolder joint reliabilityVSAvoidpackage structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent employs asymmetry by using solder joints of varying shapes (circular, square, rectangular, triangular) and sizes at different locations rather than uniform joints. This asymmetric design strategically places larger, more complex joints at stress-prone areas like corners and edges, improving reliability without uniformly increasing complexity across the entire device.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The solder joint array is segmented into multiple joints with different characteristics rather than using a single uniform joint design. This segmentation allows each joint to be optimized for its specific location's stress profile, improving overall reliability while managing complexity through modular, location-specific design rather than monolithic complexity.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The enlarged and uniquely shaped solder joints and pads significantly improve solder joint reliability by increasing the cracking path length and fatigue life under thermal and mechanical stress conditions, such as temperature cycling and drop impact.

Implementation Method 1

these substrates can become thinner as more size is needed to accommodate silicon chip volume. This can increase the deformation and stress on solder joint interfaces due to the coefficient of thermal expansion (CTE) mismatch between packages and printed circuit boards (PCB) when packages are subjected to temperature cycling

Methodology Applied
Scientific EffectCoefficient of thermal expansion mismatch: Thermal Expansion

Data Source

PatentUS20240063141A1Solder joint design for improved package reliability
Publication Date: 2024.02.22 MICRON TECHNOLOGY INC
  • US20240063141A1 patent drawing
  • US20240063141A1 patent drawing
  • US20240063141A1 patent drawing

AI summary

A semiconductor package can include a substrate having bonded thereto an array of solder joints. Each of the solder joints in the array can have a first surface area and a first shape. The semiconductor package can further include at least one differently-sized solder joint having a second surface area larger than the first surface area. The differently-sized solder joint can have a second shape different from the first shape. Other systems, methods and apparatuses are described.