Solder Limiting Layer for IC Copper Bump Stress
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Solution Overview
Problem
The microelectronics industry faces challenges with cracking and delamination of low-k interlayer dielectric (ILD) layers during the flip-chip packaging process due to shear stresses from thermal expansion mismatches and normal stresses caused by die and package warping, especially as integrated circuit dimensions scale down.
Innovation Solution
A solder limiting layer is introduced over the passivation layer and portions of the metal bumps, making the outer edges non-wettable to solder, thereby restricting the solder ball's wetting area and distributing stress more evenly across the ILD layers, reducing compressive and tensile stresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder balls are allowed to wet the entire surface of metal bumps, then good electrical connection is achieved, but stress concentration occurs at the edges causing ILD cracking and delamination
Solution Approach 1:
The patent applies local quality by creating a non-uniform wetting surface on the metal bump. The center region allows solder wetting for electrical connection, while the outer edge region has modified properties (through plasma treatment, coating, or topography) to prevent solder wetting. This spatial differentiation of wetting properties eliminates edge stress concentration while maintaining central connection quality.
Solution Approach 2:
The metal bump surface is segmented into distinct functional zones: a central wetting region for solder attachment and an outer non-wetting region for stress relief. This segmentation is achieved through selective surface treatment methods such as plasma processing, material coating, or topographical modification that creates chemically or physically distinct zones on the bump surface.
2Object-affected harmful factors
If wider metal bumps are used to reduce stress, then stress distribution improves, but bump pitch must be increased reducing circuit density
Solution Approach 1:
The invention enables narrow metal bumps to achieve the stress-distribution benefits of wider bumps by creating a localized non-wetting region at the outer edge. This allows the bump to maintain a small overall diameter for high circuit density while the non-wetting edge prevents stress concentration, effectively decoupling bump size from stress management capability.
3Ease of manufacture
If low-k dielectric materials are used for ILD layers, then manufacturing complexity and cost are reduced, but cracking and delamination resistance decreases
Solution Approach 1:
The patent applies preliminary anti-action by pre-modifying the metal bump surface properties before solder attachment to prevent the harmful wetting-induced stress concentration. Through plasma treatment, coating application, or topographical modification during fabrication, the outer edge is prepared to repel solder, thereby preemptively eliminating the stress concentration mechanism that would cause low-k ILD cracking and delamination.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution mitigates cracking and delamination issues in ILD layers by reducing stress propagation into the IC die, allowing for the use of weaker low-k materials and smaller bump pitches without inducing short circuits.
Implementation Method 1
making the outer edges non-wettable to solder, thereby restricting the solder ball's wetting area
Data Source
AI summary
An apparatus comprises a semiconductor substrate having a device layer, a plurality of metallization layers, a passivation layer, and a metal bump formed on the passivation layer that is electrically coupled to at least one of the metallization layers. The apparatus further includes a solder limiting layer formed on the passivation layer that masks an outer edge of the top surface of the metal bump, thereby making the outer edge of the top surface non-wettable to a solder material.