Solder Mask Patch Confines Bump Material for Finer Trace Pitch
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Solution Overview
Problem
The existing semiconductor manufacturing processes face challenges in minimizing the escape pitch of trace lines to achieve higher routing density, as the conventional solder mask registration openings (SRO) limit the spacing between trace lines, leading to reduced interconnect density and increased risk of electrical shorts.
Innovation Solution
The method involves forming a solder mask patch interstitially within the array of integrated bump pads on the substrate, which confines the conductive bump material during reflow, eliminating the need for SRO and allowing for closer trace line spacing without electrical shorts, thereby reducing the escape pitch and increasing routing density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder mask registration openings (SRO) are used to confine conductive bump material, then reliability is improved by preventing electrical shorts, but device complexity increases and escape pitch is enlarged reducing routing density
Solution Approach 1:
The patent extracts and eliminates the solder mask registration openings (SRO) from the conventional structure. By removing this component, the invention simplifies the device structure while maintaining bump material confinement through alternative means (self-alignment and surface tension during reflow), thereby resolving the contradiction between reliability and device complexity.
Solution Approach 2:
The invention segments the function of bump material confinement from the SRO structure. Instead of using a separate SRO component, the confinement function is achieved through the inherent properties of the reflow process and the geometric arrangement of bump pads, eliminating the need for additional structural elements.
2Reliability
If solder mask registration openings (SRO) are used to confine conductive bump material, then reliability is improved by preventing electrical shorts, but escape pitch is enlarged reducing interconnect density
Solution Approach 1:
By removing the SRO structure entirely, the patent eliminates the additional pitch space that SRO would require. The bump material is confined directly over the bump pads through self-alignment during reflow, allowing trace lines to be positioned closer together and thereby reducing escape pitch while maintaining reliability.
Solution Approach 2:
Instead of using SRO to define the confinement area, the invention inverts the approach by using the bump pads themselves as the confinement boundaries. The bump material naturally aligns with and is confined to the bump pad areas during reflow, eliminating the need for external SRO structures and reducing overall pitch requirements.
3Manufacturing precision
If solder mask registration openings (SRO) are used to confine conductive bump material, then manufacturing precision is maintained, but productivity is reduced due to increased manufacturing steps
Solution Approach 1:
The patent removes the SRO formation step from the manufacturing process. By eliminating this step, the number of manufacturing operations is reduced, thereby improving productivity. The bump material confinement precision is maintained through the self-alignment mechanism inherent in the reflow process, where molten solder naturally adheres to and is confined by the bump pad geometry.
Solution Approach 2:
The invention employs self-service by allowing the bump material to self-align and self-confine during the reflow process. The molten solder automatically adheres to the bump pads and maintains proper boundaries without requiring external SRO structures or additional manufacturing steps, thereby simplifying the process while maintaining precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a finer pitch between trace lines, enhancing interconnect density and reducing the risk of electrical failures by maintaining the conductive bump material within the defined area, thus improving the overall performance and efficiency of semiconductor devices.
Implementation Method 1
confines the conductive bump material during reflow
Data Source
AI summary
A semiconductor device has a semiconductor die having a plurality of die bump pad and substrate having a plurality of conductive trace with an interconnect site. A solder mask patch is formed interstitially between the die bump pads or interconnect sites. A conductive bump material is deposited on the interconnect sites or die bump pads. The semiconductor die is mounted to the substrate so that the conductive bump material is disposed between the die bump pads and interconnect sites. The conductive bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the semiconductor die and substrate. The solder mask patch confines the conductive bump material within the die bump pad or interconnect site. The interconnect structure can include a fusible portion and non-fusible portion. An encapsulant is deposited between the semiconductor die and substrate.