Solder Mask Thickness Control for IC Package Warpage
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Solution Overview
Problem
Flip chip semiconductor packaging faces challenges with substrate warpage and stress due to differential thermal expansion between IC and package substrates, exacerbated in 3D configurations like package on package, where stiff solder ball connections can crack or delaminate, and maintaining flat surfaces is difficult as boards heat and cool.
Innovation Solution
Controlling the average thickness and pattern of the top and bottom solder masks to manage warpage and stress levels, including varying the thickness of the solder masks and incorporating grooves or windows in the solder mask design to optimize package warpage and reliability, particularly in 3D IC packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If the package substrate is heated and cooled during operation, then thermal expansion occurs, but differential expansion between IC and substrate causes warpage and stress
Solution Approach 1:
The patent modifies the physical parameters of the solder mask layer by creating varying thicknesses (thinner at edges, thicker at center) to change its mechanical properties. This parameter change allows the solder mask to better accommodate thermal expansion differences between the IC and substrate, reducing warpage while maintaining surface flatness during thermal cycling
Solution Approach 2:
The solder mask is designed with non-uniform thickness distribution across different locations - thinner at the edges and thicker at the center. This local quality variation allows different regions of the substrate to expand and contract differently during thermal cycling, compensating for differential thermal expansion and reducing overall warpage
2Strength
If solder ball connections are made stiff for strong mechanical strength, then connection strength increases, but stress from differential expansion causes cracking or delamination
Solution Approach 1:
The patent uses a thin film structure (solder mask layer) with controlled thickness variation to provide flexibility that accommodates thermal expansion. This flexible thin film structure allows the stiff solder ball connections to maintain their strength while the surrounding solder mask absorbs expansion stress, preventing cracking and delamination
Solution Approach 2:
The solder mask layer is designed beforehand to act as a cushioning element that absorbs and distributes the stress generated by differential thermal expansion. This pre-designed stress distribution mechanism protects the stiff solder ball connections from excessive stress that would cause cracking or delamination during thermal cycling
3Productivity
If the top package is larger than the bottom package in package on package configuration, then integration density increases, but warpage likelihood increases
Solution Approach 1:
The patent applies parameter changes to the solder mask thickness distribution in package on package configurations, particularly at the edges and corners of the larger top package. By adjusting these thickness parameters, the patent compensates for the increased warpage tendency caused by the size differential between packages, maintaining flatness while achieving high integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces warpage and stress in flip chip packages, enhancing the process window and reliability, including in package on package configurations, by allowing for better coplanarity control and routability, and extending thermal cycling performance.
Implementation Method 1
If the IC and the package substrate have different coefficients of thermal expansion (CTE), differential expansion occurs when the package is heated and cooled. The differential expansion places large stress on the solder ball connections, which may cause the connections to crack or delaminate from the substrate, or cause warpage of the package substrate.
Data Source
AI summary
A method comprises determining a warpage of an integrated circuit (IC) package design. The IC package design includes a substrate having a top solder mask on a first major surface and a bottom solder mask on a second major surface opposite the first major surface. The first major surface has an IC die mounted over the top solder mask. The design is modified, including modifying an average thickness of one of the group consisting of the top solder mask and the bottom solder mask, so as to reduce the warpage. An IC package is fabricated according to the modified design.