Solder Paste Mark Setting for PCB Mounting Alignment

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Solution Overview

Problem

Existing methods for determining the misalignment of solder paste on printed circuit boards are inaccurate, leading to difficulties in correcting the mounting position of electronic components, especially when the solder paste is misaligned or larger than the land, causing potential tombstoning and misalignment issues during the reflow process.

Innovation Solution

A solder paste mark setting method and device that captures images of both solder paste and non-solder paste areas on a master printed circuit board to set accurate solder paste marks, using the ideal positions to determine misalignment and correct the mounting position of electronic components by emphasizing the different reflectance ratios and utilizing multiple solder paste areas for improved accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the mounting position of electronic component is decided by using the position of land as a reference, then the component mounting process can proceed normally, but the misalignment between solder paste and land cannot be corrected, causing tombstoning and misalignment during reflow

Engineering Contradiction:
Improvemounting position accuracyVSAvoidsolder paste position detection accuracy
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The patent creates a master printed circuit board with ideal solder paste deposits that serves as a reference copy. This master board's solder paste positions are captured and used as the standard for determining accurate mounting positions, allowing the system to correct for misalignment in production boards by comparing against this ideal reference copy.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent performs preliminary imaging and mark setting on a master printed circuit board before actual production. By capturing images of ideal solder paste positions in advance and setting reference marks, the system prepares correction data beforehand that can be applied during component mounting to prevent tombstoning and misalignment issues.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If the misalignment of solder paste is determined by comparing with land position, then the detection process is simple, but the measurement accuracy is insufficient when solder paste is misaligned or larger than land

Engineering Contradiction:
Improvedetection process simplicityVSAvoidsolder paste misalignment measurement accuracy
Core Design Contradiction:
Ease of manufactureVSMeasurement precision

Solution Approach 1:

Instead of directly measuring misalignment by comparing solder paste to land positions (which is inaccurate when paste is misaligned or larger), the patent creates a copy of the ideal solder paste pattern from the master board and uses this as the reference for measurement, thereby maintaining measurement accuracy regardless of actual paste variations.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent changes the reference parameter from land position to ideal solder paste position (captured from master board). This parameter change allows accurate misalignment measurement even when the actual solder paste deposits vary in size or position, as the reference remains based on the ideal pattern rather than the variable land geometry.

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If multiple solder paste areas are used for setting marks, then the accuracy of misalignment determination is improved, but the image processing complexity increases

Engineering Contradiction:
Improvemisalignment determination accuracyVSAvoidimage processing complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the solder paste pattern into multiple distinct areas (first, second, third, fourth areas) and processes each area separately to determine its center position. This segmentation allows accurate misalignment calculation by averaging or comparing multiple reference points, improving overall measurement precision while keeping each individual processing step manageable.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for precise determination and correction of solder paste misalignment, enhancing the accuracy of electronic component mounting and reducing the risk of tombstoning and misalignment, even with imperfect solder paste deposits.

Implementation Method 1

illuminate the image area with light falling perpendicular onto the image area, and use the different reflectance ratios of the area on which solder paste is deposited and area on which solder paste is not deposited

Methodology Applied
Scientific EffectReflection: Reflection

Data Source

PatentEP2717665B1Solder mark setting method and solder mark setting device
Publication Date: 2017.06.21 FUJI CORP
  • EP2717665B1 patent drawingFigure 1
  • EP2717665B1 patent drawingFigure 2
  • EP2717665B1 patent drawingFigure 3

AI summary

The present invention relates to a solder paste mark setting method and solder paste mark setting device which make it possible to accurately determine the misalignment amount of the solder paste and to accurately correct the mounting position of an electronic component. The solder paste mark setting method consists of an imaging process in which an image is taken of areas G4, G5 which contain solder paste areas (on which solder paste is deposited) Ea1, Ea2, Eb-ed and non solder paste areas (on which solder is not deposited) of a master printed circuit board Bf0 on which solder paste has been deposited to specific positions on lands Da1, Da2, Db-Dd of the circuit pattern Ca1, Ca2, Cb-Cd and in which image g4 of areas G4 and G5 is acquired; and of a setting process in which solder paste areas Ea1, Ea2, Eb-Ed are extracted from image g4 and in which solder marks Em0 are set on the master printed circuit board Bf0.