Self-Aligned Solder Reflow Bonding for 3D Semiconductor Stacking
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Solution Overview
Problem
Current 3D semiconductor packaging technologies face limitations in downscaling interconnects due to alignment accuracy issues and pressure requirements during bonding, which hinder the use of thinner devices with smaller pitches and increase the risk of device damage.
Innovation Solution
A solder reflow-based self-aligned bonding method that eliminates the need for pressure during bond formation, utilizing a first semiconductor device with a dielectric layer and metal-lined hole and a second device with a compliant layer and metal protrusion, where the protrusion is landed in the hole and solder is reflowed to form a void-free interface, allowing for fine pitch stacking without underfill material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If pressure is applied during bonding to ensure reliable connection, then bond strength is improved, but thinner semiconductor devices are damaged
Solution Approach 1:
The patent utilizes the phase transition of solder material from solid to liquid state during reflow bonding. The solder is heated to melt and form a eutectic liquid phase that wets and bonds the metal surfaces, then cooled to solidify into a strong joint. This phase transition enables bonding without applying mechanical pressure to the thin semiconductor devices, resolving the contradiction between achieving strong bonds and preventing device damage.
2Manufacturing precision
If alignment accuracy is improved to enable smaller pitches, then manufacturing precision is improved, but equipment complexity increases
Solution Approach 1:
The patent implements self-aligned bonding where the solder material automatically positions itself during the reflow process. The liquid solder wets the metal surfaces and forms bonds at the correct locations through capillary action and surface tension, eliminating the need for highly complex alignment equipment. This self-service mechanism achieves precise alignment without increasing equipment complexity.
3Productivity
If device thickness is reduced to enable higher stacking counts, then productivity is improved, but device damage risk increases
Solution Approach 1:
By utilizing solder phase transition during reflow bonding, the patent enables connection of thinned semiconductor devices without applying mechanical pressure. The liquid solder flows to create bonds while the devices remain in a low-stress state, allowing devices to be thinned to greater extents for higher stacking counts without increased damage risk.
4Ease of manufacture
If solder material is used for bonding, then ease of manufacture is improved, but void formation occurs reducing bond reliability
Solution Approach 1:
The patent utilizes the phase transition of solder from solid to liquid and back to solid in a controlled reflow process. The solder is heated to melt completely, allowing voids to rise and escape during the liquid phase, then cooled to solidify into a dense, void-free bond. This controlled phase transition maintains ease of manufacture while eliminating void formation that would reduce reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method achieves inherent self-alignment, prevents device damage, ensures void-free bonds, and absorbs compressive stress, enabling the stacking of thinner devices with smaller pitches while maintaining low temperature processing and improving bond reliability.
Implementation Method 1
reflowing the solder material, thereby bonding the devices
Implementation Method 2
heating the solder material to a reflow temperature
Implementation Method 3
the compliant layer absorbs the compressive stress, that exists after the solder reflow
Implementation Method 4
a capping layer protects the protrusions from oxidation prior to and during the formation of the stack
Data Source
AI summary
A method for producing a stack of semiconductor devices and the stacked device obtained thereof are disclosed. In one aspect, the method includes providing a first semiconductor device comprising a dielectric layer with a hole, the hole lined with a metal layer and partially filled with solder material. The method also includes providing a second semiconductor device with a compliant layer having a metal protrusion through the compliant layer, the protrusion capped with a capping layer. The method further includes mounting the devices by landing the metal protrusion in the hole, where the compliant layer is spaced from the dielectric layer. The method includes thereafter reflowing the solder material, thereby bonding the devices such that the compliant layer is contacting the dielectric layer.