Solder Resist Layout for Crack-Resistant Embedded Die Packaging
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Solution Overview
Problem
Conventional embedded die packaging for high voltage/high current power semiconductor devices, such as GaN HEMTs, faces reliability issues due to degradation of dielectric materials under high electric fields and extreme thermal cycling, particularly with solder resist layers that are susceptible to mechanical, thermal, and electrical stress.
Innovation Solution
The packaging is improved by patterning the external dielectric coating, such as solder resist, to avoid inside corners and instead use outside corners or radiused corners, minimizing stress and preventing crack initiation and propagation during thermal cycling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional solder resist layers are used to provide external dielectric coating and protective layer, then electrical insulation and protection are achieved, but reliability deteriorates under high electric fields and elevated temperatures due to susceptibility to degradation
Solution Approach 1:
The patent removes the solder resist layer from areas surrounding contact pads, extracting the problematic dielectric material from high-stress regions. This selective removal eliminates the source of degradation while maintaining solder resist in areas where it provides necessary protection and insulation, thus resolving the contradiction between protection and reliability under extreme conditions.
Solution Approach 2:
The patent applies different dielectric configurations to different locations: solder resist is maintained in some areas and removed in others. Specifically, the solder resist is removed from areas surrounding contact pads where high electric fields and thermal stress cause degradation, while retaining it in areas where it provides beneficial protection. This local differentiation optimizes reliability by matching material presence to local stress conditions.
2Reliability
If solder resist is applied as conformal coating by screen-printing, then coverage is improved, but bubbles or voids form leading to reliability issues
Solution Approach 1:
The patent removes solder resist from areas surrounding contact pads, eliminating regions where screen-printing processes would trap bubbles and voids. By extracting the solder resist material from these high-risk zones, the patent prevents the formation of harmful voids that would compromise reliability, while maintaining solder resist in areas where the conformal coating process is less problematic.
3Reliability
If solder resist extends over edges or corners of underlying metal interconnect, then coverage is improved, but mechanical, thermal, and electrical stress and damage increase
Solution Approach 1:
The patent removes solder resist from areas surrounding contact pads and metal interconnect edges, extracting the material that would otherwise concentrate stress. This elimination prevents the accumulation of mechanical, thermal, and electrical stress in corner and edge regions, thereby improving reliability under high-voltage and high-temperature operating conditions.
Solution Approach 2:
The patent implements location-specific solder resist placement: removing it from high-stress regions around metal interconnect edges and contact pads, while retaining it in areas where it provides protection without significant stress concentration. This local quality differentiation reduces overall stress on the package structure.
Data Source
AI summary
Embedded die packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a power semiconductor die is embedded in package body comprising dielectric layers and electrically conductive layers, and where an external dielectric coating, such as a solder resist coating is provided on one or both external sides of the package body. The solder resist coating is patterned to avoid inside corners, e.g. the solder resist does not extend around or between electrical contact areas and thermal pads. It is observed that in conventional solder resist coatings, during thermal cycling, cracks tend to initiate at high stress points, such as at sharp inside corners. A solder resist layout which omits inside corners, and comprises outside corners only, is demonstrated to provide significantly improved resistance to initiation and propagation of cracks. Where inside corners are unavoidable, they are appropriately radiused to reduce stress.