Solder Resist Pattern for Semiconductor Module Stress Distribution
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Solution Overview
Problem
The reliability of semiconductor modules is compromised due to the peeling or fracturing of solder bonding portions on printed wiring boards, especially when subjected to mechanical stress from drops or thermal expansion, as existing designs fail to distribute stress evenly and prevent localized concentration on corner solder bonding portions.
Innovation Solution
The design incorporates a solder resist pattern on the printed wiring board that covers specific edge portions of lands, creating a combination of Solder Mask Defined (SMD) and Non-Solder Mask Defined (NSMD) structures to distribute thermal stress and prevent peeling, while ensuring sufficient bonding strength by optimizing the area exposed and covered by the solder resist.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If solder bonding portions are made smaller to downsize semiconductor devices, then device size is reduced, but solder bonding portions may peel off or fracture in normal use
Solution Approach 1:
The patent applies different structures to different parts of the land: corner lands have solder resist covering all four edge portions, while inner lands have solder resist covering only two edge portions. This local differentiation allows corner lands (which experience higher stress during drop) to have enhanced peeling resistance, while maintaining overall device downsizing.
Solution Approach 2:
The land structure is segmented into corner lands and inner lands with different solder resist coverage patterns. Corner lands are further segmented into four edge portions, with selective coverage to optimize both mechanical strength and solder bonding area.
Data Source
AI summary
A semiconductor module includes a printed wiring board and a semiconductor device. The printed wiring board includes a plurality of lands bonded to the semiconductor device via solder, and a solder resist. The plurality of lands includes a first land positioned in a vicinity of an outer edge of the insulating substrate and including a first edge portion, a second edge portion, a third edge portion, and a fourth edge portion. The first edge portion and the second edge portion are configured not to overlap with the solder resist and the third edge portion and the fourth edge portion are configured to overlap with the solder resist.