Solder Resist Layer Warpage Correction in IC Packaging

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Solution Overview

Problem

The miniaturization of integrated circuit packages faces challenges such as warpage due to CTE mismatch, making it difficult to meet coplanarity specifications, and multi-chip modules require individual chip testing before assembly, which is inefficient and prone to assembly defects.

Innovation Solution

A method involving a solder resist layer with specific CTE and curing shrinkage characteristics is applied to the package substrate, patterning access openings and a die mount opening, allowing for controlled coplanarity of system interconnects and conductive contacts, enabling warpage correction and individual chip testing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If thinner package substrates are used to achieve miniaturization, then package size is reduced, but warpage occurs due to CTE mismatch making it difficult to meet coplanarity specifications

Engineering Contradiction:

Improvepackage sizeVSAvoidcoplanarity specification

Core Design Contradiction:

Volume of moving objectVSManufacturing precision

Solution Approach 1:

The patent applies a solder resist layer with specific thickness (5-20 micrometers) and controlled curing shrinkage characteristics to modify the thermal expansion parameters of the package substrate. This layer compensates for the CTE mismatch between chip and substrate, correcting warpage and enabling coplanarity specifications to be met while maintaining thin package dimensions

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent creates a composite structure by depositing a solder resist layer on the package substrate. This composite material system combines the substrate material with the solder resist layer having different CTE properties, creating a balanced structure that reduces warpage while maintaining the overall thin profile required for miniaturization

Inventive Principle:

Principle #40Composite materials

2Area of stationary object

If multi-chip modules are assembled before chip testing, then board space is reduced, but assembly defects increase due to inability to identify defective chips

Engineering Contradiction:

Improveboard spaceVSAvoidassembly process yield

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The patent enables preliminary testing of individual chips before final assembly into multi-chip modules. By providing access openings in the solder resist layer, test probes can access chip bond pads to perform electrical testing, allowing defective chips to be identified and replaced before final assembly, thus improving yield while maintaining compact board space

Inventive Principle:

Principle #10Preliminary action

3Productivity

If access openings are added to the solder resist layer for testing, then individual chip testing becomes possible, but the structure becomes more complex

Engineering Contradiction:

Improvetesting efficiencyVSAvoidsubstrate structure

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the solder resist layer to create specific access openings at strategic locations. These openings provide access to chip bond pads for testing while maintaining the integrity of the overall solder resist layer. The segmented approach allows targeted access without requiring complete removal or complex patterning of the entire resist layer

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively corrects warpage and ensures coplanarity, allowing for reliable individual chip testing and assembly, enhancing the efficiency and reliability of integrated circuit packaging systems.

Implementation Method 1

warpage of the package substrate has become a significant limitation making it difficult to meet typical coplanarity specifications for such packages. In particular, for technology in which flip chip interconnection is employed to interconnect the chip to the package substrate, warpage of the package substrate has become a significant limitation

Methodology Applied

Scientific EffectCTE (coefficient of thermal expansion) mismatch: Thermal Expansion

Implementation Method 2

depositing a solder resist layer on the component side of the package substrate; controlling a coplanarity of the system interconnects by the solder resist layer

Methodology Applied

Scientific EffectCuring shrinkage: Thermal Contraction

Data Source

PatentUS9299648B2Integrated circuit packaging system with patterned substrate and method of manufacture thereof

Publication Date: 2016.03.29 STATS CHIPPAC LTD

AI summary

A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a component side and a system side; depositing a solder resist layer on the component side of the package substrate; patterning groups of access openings and a die mount opening in the solder resist layer; attaching an integrated circuit die in the die mount opening; forming conductive contacts in the access openings; and attaching system interconnects to the system side of the package substrate including controlling a coplanarity of the system interconnects by the solder resist layer.