Solder Stud Structure for Fine Pitch Flip Chips
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Solution Overview
Problem
Existing bond pads in semiconductor devices are not entirely satisfactory as device scaling-down continues, particularly due to limitations in controlling shape and stress, and require reflow processes that restrict their application in miniaturized circuits.
Innovation Solution
The formation of a solder stud without a reflow process, allowing precise control over its shape and size, which can be a tetragon, trapezoid, or rectangle with controlled angles and dimensions, enabling it to be used for bonding with conductive posts without the need for additional conductive pillars.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing bond pads are used for device interconnection, then electrical connections can be established, but the shape and size cannot be precisely controlled and reflow processes are required
Solution Approach 1:
The patent changes the material parameter from traditional bond pad materials to solder material, which enables precise shape and size control through controlled formation processes without requiring reflow processing. This parameter change allows the solder stud to be formed with specific geometries (cylindrical, conical, or other shapes) directly during the deposition process.
Solution Approach 2:
The patent performs preliminary action by forming the solder stud with controlled shape and size before the bonding process. The solder stud is deposited and patterned to precise dimensions in advance, eliminating the need for subsequent reflow processing to achieve the desired geometry. This preliminary formation of precise structures resolves the contradiction between manufacturing precision and process complexity.
2Adaptability or versatility
If reflow processes are used for bond pad formation, then bonding can be achieved, but applications in miniaturized circuits are restricted
Solution Approach 1:
The patent extracts the reflow process from the bond pad formation sequence by using solder material that can be directly deposited and patterned to final shape without requiring thermal reflow. This removal of the reflow step simplifies the process and enables application in miniaturized circuits where reflow would be problematic, thereby increasing adaptability without adding device complexity.
Solution Approach 2:
The patent employs a disposable-like approach by using a sacrificial layer (photoresist or hard mask) that is removed after defining the solder stud pattern. This allows precise shape control through simple deposition and etching processes without complex reflow equipment, making the solution adaptable to miniaturized circuits while keeping the process relatively simple.
3Reliability
If additional conductive pillars are added for bonding, then connection reliability is improved, but device complexity and cost increase
Solution Approach 1:
The patent makes the solder stud multi-functional by designing it to simultaneously provide both the bonding interface and the conductive connection path. The solder stud serves dual purposes: as the bonding element that joins to the conductive post and as the conductive pathway for electrical signals. This eliminates the need for separate additional conductive pillars, maintaining reliability while reducing structure complexity.
Solution Approach 2:
The patent merges the bonding function and conductive function into a single solder stud structure. Instead of having separate bonding elements and conductive pillars, the solder stud combines both functions, directly connecting the bond pad to the conductive post while providing electrical connectivity. This merging reduces device complexity and cost while maintaining connection reliability.
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes a first substrate and a metal pad formed over the first substrate. The semiconductor structure further includes a solder stud formed over the metal pad, and the solder stud has a flat top surface parallel to a top surface of the first substrate.