Solder on Trace Device for Fine Pitch Flip Chip Reliability

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Solution Overview

Problem

Fine pitch flip chip technology faces challenges in providing reliable semiconductor substrate pad to die bump joints due to insufficient confined wetting surfaces for solder bumps, leading to issues like voiding and open circuits caused by uncontrolled solder wetting.

Innovation Solution

The implementation of a solder on trace device with a conductive trace having a sidewall and bonding surface, featuring a passivation layer and pre-solder material applied only to the active bonding area, allowing for selective wetting and bonding with solder balls or pillars, using a dry film stencil printing process for precise pitch control and volume tolerance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a surface finish is applied to the entire trace/pad to enable solder ball connection, then the solder ball connection is enabled, but the solder may wet through the entire trace beyond the specific bond area, causing open circuits and bridging

Engineering Contradiction:
Improvesolder ball connection reliabilityVSAvoiduncontrolled solder wetting causing open circuits and bridging
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies surface finish (e.g., electroplated copper, nickel, or tin) only to the specific bond area of the trace where solder ball connection is required, rather than the entire trace. This localized treatment enables reliable solder attachment at the intended location while preventing unwanted solder wetting and bridging on other portions of the trace, thus resolving the contradiction between achieving good solder connection and avoiding harmful uncontrolled wetting.

Inventive Principle:
Principle #3Local quality

2Reliability

If flux material is applied on oxidized portion of trace/pad to reactivate the surface for solder connection, then the trace reactivity is improved, but outgassing of flux material causes voiding in the process

Engineering Contradiction:
Improvetrace to solder connection reliabilityVSAvoidflux outgassing causing voids
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent performs preliminary surface preparation by applying surface finish to the trace before solder ball attachment, creating a reactive, oxidation-resistant surface in advance. This preliminary action eliminates or minimizes the need for flux material during the soldering process, thereby preventing flux outgassing and void formation while still achieving reliable solder connection to the trace.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If fine pitch flip chip technology is used to achieve smaller pitch range, then the integration density is improved, but sufficient and reliable semiconductor substrate pad to die bump joints cannot be provided due to inability to provide confined wetting surface

Engineering Contradiction:
Improveintegration densityVSAvoidpad to bump joint reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements localized surface finish treatment on specific bond areas of the substrate traces, creating confined wetting surfaces that precisely control where solder balls attach. This localized treatment enables reliable solder joints even at fine pitch dimensions by ensuring solder confinement to intended locations, thus resolving the contradiction between achieving high integration density through fine pitch and maintaining reliable pad-to-bump joints.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables reliable fine pitch flip chip designs with improved solder confinement, reducing the risk of shorts and enhancing the reliability of semiconductor connections by activating only the specific bond area for solder interconnects, achieving a pitch range of 20 to 120 microns.

Implementation Method 1

a pre-solder material on the sidewall and bonding surface of the conductive trace

Methodology Applied
Scientific EffectWetting: Wetting

Implementation Method 2

The pre-solder material on the sidewall and bonding surface of the conductive trace enables wetting and bonding with solder balls or pillars

Methodology Applied
Scientific EffectAdhesion: Adhesive

Implementation Method 3

a passivation layer on at least one end of the conductive trace

Methodology Applied
Scientific EffectOxidation prevention: Oxidation

Data Source

PatentUS9461008B2Solder on trace technology for interconnect attachment
Publication Date: 2016.10.04 QUALCOMM INC
  • US9461008B2 patent drawing
  • US9461008B2 patent drawing
  • US9461008B2 patent drawing

AI summary

A solder on trace device includes a conductive trace on a semiconductor substrate surface. The conductive trace has a sidewall and a bonding surface. The solder on trace device also includes a passivation layer on at least one end of the conductive trace. The solder on trace device further includes a pre-solder material on the sidewall and the bonding surface of the conductive trace.