Solder Void Reduction on Circuit Boards via Via Hole Coating
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Solution Overview
Problem
Voids form at solder connection points on circuit boards due to trapped air in via holes, which expands during the reflow process, reducing the solder surface area and increasing the likelihood of premature electrical or mechanical failure.
Innovation Solution
A non-conductive coating is applied to the circuit board, with specific areas left uncovered to expose conductive landing pads, while via holes are covered to prevent gas expansion and void formation, using a screen or photo mask to control the coating application and removal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If via holes are left uncovered at conductive landing pads, then gas can escape during reflow, but voids form in the solder joints reducing reliability
Solution Approach 1:
The patent converts the harmful effect of trapped gas (which causes voids) into a beneficial outcome by using the gas pressure to push solder into the via holes during reflow. The coating is temporarily removed to allow gas escape paths, but positioned to direct gas flow in a way that promotes solder filling rather than void formation. This transforms the harmful gas expansion into a useful force that improves solder joint quality.
Solution Approach 2:
The patent introduces a coating material as an intermediary between the via hole and the solder. This coating acts as a mediator that controls gas flow and solder wetting. By selectively removing portions of the coating, the system mediates between the need to trap gas (to prevent voids) and the need to allow gas escape (to prevent pressure buildup), achieving optimal solder joint formation.
2Object-generated harmful factors
If coating is applied over via holes to prevent gas expansion, then void formation is reduced, but conductive landing pad area is reduced
Solution Approach 1:
The patent applies local quality by differentiating the coating treatment across different regions of the conductive landing pad. Instead of uniformly coating or leaving uncovered, the coating is selectively applied to specific areas (such as peripheral regions or specific via locations) while leaving other areas exposed. This localized approach allows gas management in critical regions while preserving solder contact area in other regions, thereby reducing voids without significantly reducing overall conductive landing pad area.
3Area of stationary object
If selective coating removal is performed to expose landing pads, then solder contact area is maximized, but void formation increases
Solution Approach 1:
The patent applies preliminary action by pre-positioning the coating material in specific patterns before the soldering process. The coating is applied and then selectively removed in advance, creating predetermined gas management structures that guide solder flow and gas escape during reflow. This preliminary configuration ensures that when soldering occurs, the landing pad geometry is already optimized to prevent void formation while maximizing contact area, eliminating the need for real-time adjustments during soldering.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method significantly reduces void formation, increasing the solder connection surface area and improving both mechanical and electrical reliability of the solder joints without requiring additional processing steps.
Implementation Method 1
covering at least some of the via holes with a coating, whereby gases from the covered via holes are prevented from expanding and forming voids
Implementation Method 2
exposing areas of the coating at the conductive landing pad left uncovered by the screen to a chemical etching agent; and removing the coating from areas of the conductive landing pad exposed to the chemical etching agent
Data Source
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AI summary
There is disclosed a method, system, and screen for reducing solder voids on circuit boards. In an embodiment, there is provided a method of reducing solder voids on a circuit board, comprising: locating via holes provided at a conductive landing pad; and covering at least some of the via holes with a coating, whereby gases from the covered via holes are prevented from expanding and forming voids. In another embodiment, the method further comprises covering the location of at least some of the via holes in a pattern of strips, whereby more of the via holes may be covered by the coating while reducing areas of the conductive landing pad covered by the coating. In another embodiment, the coating and removal process may be performed at the same time as when all other areas of the circuit board are coated and removed, such that a separate manufacturing step is not required.