Solderless 3D Chip Stack Using Noble Metal Bonding
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Solution Overview
Problem
Traditional chip stacking methods using solder joints face limitations in pitch, joint height, and flux residue, and require a carrier substrate larger than the chips, which hinders the advancement of high-wiring density in compact packages.
Innovation Solution
The use of solderless bonding metallurgy, such as gold-to-gold or noble metal-to-noble metal bonding between metal pillars and pads on semiconductor chips, eliminates the need for solder and flux, allowing for a low-temperature, low-pressure bonding process without ultrasonic assistance, and forms a solderless joining structure with noble metals like gold or its alloys.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional solder joint methods are used for chip stacking, then electrical connections can be formed between chips, but pitch is limited, joint height is constrained, and flux residue issues arise
Solution Approach 1:
The patent extracts and eliminates solder and flux from the bonding process entirely. Instead of using traditional solder joints with flux, the invention employs direct metal-to-metal bonding between copper pillars on one chip and copper pads on another chip, removing the source of flux residue problems while enabling finer pitch joining
Solution Approach 2:
The patent replaces the thermal-mechanical soldering process with a mechanical direct bonding process. Copper pillars are bonded directly to copper pads through pressure and potentially ultrasonic assistance, eliminating the need for flux and enabling precise control of pitch and joint height without flux residue contamination
2Reliability
If carrier substrate is used for wire bonding, then electrical connections can be established, but the substrate must be larger than the chips, increasing package size
Solution Approach 1:
The patent merges the electrical connection function directly into the chip stacking structure itself. By forming copper pillars and pads that directly bond chips together, the electrical interconnection is integrated into the mechanical stack, eliminating the need for a separate carrier substrate and enabling compact packaging where the chip stack is the final package form
Solution Approach 2:
The patent transitions from planar wire bonding on a large substrate to vertical three-dimensional chip stacking. Electrical connections are established in the vertical dimension through direct chip-to-chip bonding, allowing high wiring density in a compact vertical architecture rather than requiring a large horizontal substrate area
3Productivity
If flip-chip interconnections with conductive balls are used, then high wiring density is achieved in small package, but bonding failures and reliability issues occur
Solution Approach 1:
The patent changes the material parameters of the interconnection structures by using copper pillars and pads instead of conductive balls. This material parameter change enables direct metal-to-metal bonding with superior mechanical strength and electrical conductivity, achieving high wiring density while eliminating bonding failures associated with spherical interconnections
Solution Approach 2:
The patent employs composite interconnection structures consisting of copper pillars with optional protective coatings (such as nickel or palladium) bonded to copper pads. This composite approach provides both the mechanical strength needed for reliable bonding and the electrical conductivity required for high-performance interconnections, achieving high wiring density without bonding failures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables fine pitch joining, reduces bonding failures, and achieves high electrical bonding strength while allowing for a compact, high-yield chip stacking process with reduced stand-off height, thus overcoming the limitations of traditional methods.
Implementation Method 1
The first chip is bonded to the second chip by attaching the first bump structure to the second bump structure to form a solderless joining structure
Data Source
AI summary
A three dimensional (3D) chip stack includes a first chip bonded to a second chip. The first chip includes a first bump structure overlying the first substrate, and the second chip includes a second bump structure overlying the second substrate. The first bump structure is attached to the second bump structure, and a joining region is formed between the first bump structure and the second bump structure. The joining region is a solderless region which includes a noble metal.