Solid-State Battery Chip Geometry for Low-Resistance Current Collection
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Solution Overview
Problem
All solid batteries face challenges in achieving favorable rate characteristics due to reduced current collection efficiency and increased electrical resistance when the thickness of the electric collector layer is minimized, often resulting in degraded responsiveness and potential malfunctions.
Innovation Solution
The design involves a multilayer chip with alternately stacked solid electrolyte and electrode layers, using a phosphoric acid salt-based solid electrolyte with a NASICON structure, and Pd-based electric collector layers, where the length-to-width ratio (L/W) of the chip is maintained between 0.2 and 1.1 to optimize current collection and reduce electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the thickness of the electric collector layer is reduced, then capacity density is improved, but current collection efficiency deteriorates
Solution Approach 1:
The patent changes the geometric configuration of the multilayer chip from a conventional shape to a specific rectangular parallelepiped shape with controlled L/W ratio (0.2 ≤ L/W ≤ 1.1). This dimensional optimization allows the electric collector layer to maintain adequate current collection efficiency even at reduced thickness by optimizing the current path length and cross-sectional area for electron transport.
2Quantity of substance
If the thickness of the electric collector layer is reduced, then capacity density is improved, but electrical resistance increases
Solution Approach 1:
The patent optimizes the L/W ratio of the rectangular parallelepiped multilayer chip to balance the cross-sectional area and current path length. This dimensional control ensures that even when the electric collector layer thickness is reduced, the overall electrical resistance remains acceptable due to the optimized geometry that minimizes electron transport path length while maintaining sufficient cross-sectional area.
3Quantity of substance
If the thickness of the electric collector layer is reduced, then capacity density is improved, but responsiveness deteriorates
Solution Approach 1:
The patent controls the L/W ratio within 0.2 ≤ L/W ≤ 1.1 to optimize the electrical resistance and current collection efficiency. This dimensional optimization directly improves responsiveness (rate characteristic) by minimizing the electrical resistance that would otherwise slow down electron transport, while still allowing the electric collector layer thickness to be reduced for higher capacity density.
4Speed
If the L/W ratio is optimized, then rate characteristic is improved, but manufacturing constraints increase
Solution Approach 1:
The patent defines a specific range for the L/W ratio (0.2 ≤ L/W ≤ 1.1) that balances performance and manufacturability. This parameter optimization ensures favorable rate characteristic while maintaining ease of manufacture, as the range is wide enough to accommodate normal manufacturing variations but specific enough to ensure optimal electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the rate characteristic and capacity density of the all solid battery, while maintaining structural integrity and preventing issues like delamination and cracking, thereby ensuring stable performance and high transverse strength.
Implementation Method 1
a multilayer chip in which each of a plurality of solid electrolyte layers and each of a plurality of electrodes are alternately stacked, a main component of the solid electrolyte layers being phosphoric acid salt-based solid electrolyte
Data Source
AI summary
An all solid battery includes: a multilayer chip in which each of solid electrolyte layers and each of electrodes are alternately stacked, a main component of the solid electrolyte layers being phosphoric acid salt-based solid electrolyte, the plurality of electrodes being alternately exposed to a first end face and a second end face of the multilayer chip, a first external electrode provided on the first end face; a second external electrode provided on the second end face; and wherein L/W is 0.2 or more and 1.1 or less, when a length of the multilayer chip in a first direction in which the first end face faces with the second end face is L, and a width of the multilayer chip in a second direction that is vertical to the first direction and a stacking direction of the multilayer chip is W.