Selective Erasure of Solid-Electrolyte Memory Cells
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing solid-electrolyte semiconductor memories lack selective access to individual memory cells during erasure operations due to the wide distribution of erasure voltages, leading to unintentional reprogramming of other cells.
Innovation Solution
The semiconductor memory employs a method where first and second lines are electrically biased to selectively erase a memory cell by applying distinct potentials to the lines connected to the selected cell, while other lines are biased with different voltages to prevent unintended erasure or programming of adjacent cells, ensuring that only the selected cell is erased.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a voltage is applied to erase memory cells in solid-electrolyte semiconductor memories, then erasure operation is achieved, but unintentional reprogramming of other cells occurs due to wide distribution of erasure voltages
Solution Approach 1:
The patent segments the voltage application strategy by dividing the memory array into selected and non-selected cells. Different voltage levels are applied to different segments: high voltage (above erasure threshold) to the selected cell for erasure, and low voltage (below erasure threshold) to non-selected cells to prevent unintentional reprogramming. This segmentation resolves the contradiction by enabling selective erasure while protecting other cells.
Solution Approach 2:
The patent applies local quality by making the electrical characteristics (voltage levels) location-dependent within the memory array. The selected memory cell receives a specific high voltage level for erasure, while non-selected cells receive different low voltage levels that prevent unwanted operations. This local differentiation allows reliable selective access during erasure operations.
2Reliability
If high voltage is applied to ensure complete erasure of selected cell, then erasure reliability is improved, but other cells connected to the same lines are also affected
Solution Approach 1:
The patent segments the voltage distribution by applying high voltage only to the selected cell through coordinated control of bit lines and word lines, while maintaining low voltage on non-selected cells. This is achieved by applying voltage to only one line (bit line or word line) connected to the selected cell while keeping the other line at low voltage, ensuring complete erasure of the target cell without affecting adjacent cells.
Solution Approach 2:
The patent changes the voltage parameter dynamically based on cell selection status. The selected cell experiences voltage above the erasure threshold for complete erasure, while non-selected cells experience voltage below the erasure threshold to prevent side effects. This parameter change strategy ensures both erasure reliability and protection of adjacent cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the first time selective erasure of individual solid-electrolyte memory cells without affecting other cells, maintaining the memory state of the remaining cells and preventing unintentional reprogramming.
Implementation Method 1
metal ions coming from the metallic layer diffuse either into the layer from the solid electrolyte, or from the latter back into the metallic layer
Implementation Method 2
The layer stack, which is arranged between a bit line and a word line, respectively, has a current flowing through it when the voltage is applied between the bit line and the word line
Data Source
AI summary
In integrated semiconductor memories whose stored information is represented by the magnitude of the ohmic resistance of layer stacks with a respective layer comprising a solid electrolyte, the problem arises that although the fact that the large threshold values (G1, G2) for the writing voltage and the erasure voltage differ from memory cell to memory cell means that the memory cells can be programmed individually, said memory cells cannot conventionally be erased individually, i.e., selectively in relation to the other memory cells. The reason for this is the large bandwidth of the threshold values (G1) for the erasure voltages, which ranges from a potential (Verasemin) to a potential (Verasemax). The invention proposes a semiconductor memory and a method for operating the latter, in which simultaneous biasing of all the bit lines and word lines and a specific choice of the electrical potentials allow a single memory cell to be erased selectively in relation to the other memory cells.