Solid Electrolyte Patterning Using an Amorphous Silicon Mask
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Solution Overview
Problem
Existing methods for patterning layers in solid state microbatteries, such as masking techniques, can lead to particle contamination, substrate scratching, poor alignment, and adverse effects on the interface quality between layers, particularly when etching is required.
Innovation Solution
A method involving a stack of layers where a second layer with at least 95 atomic % amorphous silicon is used as an etching mask to pattern the solid electrolyte layer, maintaining the quality of the interface and avoiding contamination or degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If masking techniques are used to pattern layers, then discrete layer elements can be formed, but particle contamination and substrate scratching occur
Solution Approach 1:
The patent removes the masking step entirely from the process. Instead of depositing layers through a shadow mask, the invention forms discrete layer elements by selectively removing material from continuous layers using etching processes. This extraction of the masking operation eliminates the source of particle contamination and substrate scratching while maintaining the ability to form discrete battery elements.
Solution Approach 2:
The patent inverts the conventional approach: instead of using a mask to define where material should be deposited, the invention deposits continuous layers and then uses etching to remove material where it should not be present. This inversion replaces the mechanical masking process with a chemical/physical etching process that avoids contamination and damage.
2Object-affected harmful factors
If etching is used to pattern layers individually, then masking techniques are avoided, but interface quality between layers deteriorates
Solution Approach 1:
The patent performs etching operations on all layers before subsequent layer depositions. By etching the current layer first and then depositing the next layer, the interface between etched and deposited layers is maintained without contamination. This preliminary action ensures that the surface to be etched is clean and that subsequent depositions occur on freshly etched surfaces, preserving interface quality.
Solution Approach 2:
The patent maintains a continuous process flow where etching and deposition operations are performed in sequence without breaking the vacuum or exposing surfaces to contamination. The useful action of creating clean interfaces is sustained throughout the multi-layer fabrication process by continuously etching before each deposition, ensuring high interface quality throughout.
3Manufacturing precision
If masking is used for small microbattery sizes, then patterning is achieved, but edge or shadow effects cause poor alignment and wasted areas
Solution Approach 1:
The patent replaces the mechanical shadow mask system with a chemical/physical etching system. Instead of relying on the physical geometry of a mask that creates edge and shadow effects, the invention uses etching processes that can achieve precise pattern definition through chemical reactions and plasma processes, eliminating the optical and geometric limitations of masking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces contamination and interface degradation, allowing for the production of high-quality discrete layer elements for solid state microbatteries while maintaining the functionality of amorphous silicon as an anode material.
Implementation Method 1
removing a through-thickness portion of the second layer to form a second discrete layer element provided by the second material
Implementation Method 2
etching the third layer using the second discrete layer element as an etching mask
Data Source
AI summary
A method of processing a stack of layers to provide a stack of discrete layer elements, comprises the steps of: providing a stack of layers comprising: #a first layer (20) provided by a first material; #a third layer (16) provided by a solid electrolyte; and #a second layer (18) located between the first and third layers, the second layer having a thickness of at least 500 nm and being provided by a second material comprising at least 95 atomic % amorphous silicon; removing a through-thickness portion of the first layer (20) to form a first discrete layer element (20a) provided by the first material; removing a through-thickness portion of the second layer (18) to form a second discrete layer element (18a) provided by the second material, the second discrete layer element being located between the first discrete layer element (20a) and the solid electrolyte; and etching the third layer (16) using the second discrete layer element (18a) as an etching mask, to form a third discrete layer element (16a) provided by the solid electrolyte; wherein the first, second and third discrete layer elements provide the stack of discrete layer elements.