Solid Electrolytic Capacitor Planar Mount Board Design
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Solution Overview
Problem
Existing solid electrolytic capacitors face challenges in reducing equivalent series resistance (ESR) and equivalent series inductance (ESL) due to large distances between capacitance formation parts and outer electrodes, making it difficult to produce thin capacitors with low ESR and ESL.
Innovation Solution
The design includes a capacitor element with a valve-acting metal substrate, a porous part, a dielectric layer, a solid electrolyte layer, and conductive layers, where the sealing resin and cathodic outer electrode are positioned on top of the conductive layer, with via electrodes penetrating the resin to reduce distance and increase the ratio of capacitance formation volume, allowing for a thin, low-ESR, low-ESL capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a plurality of capacitor elements are stacked on top of one another with traditional lead frame connection, then the capacitor can be assembled, but the distance between the capacitance formation part and outer electrode becomes large, resulting in high ESR and ESL
Solution Approach 1:
The patent transitions from a traditional stacked configuration with vertical lead frame connections to a planar configuration where capacitor elements are arranged side-by-side and connected to a mount board. This dimensional change allows the outer electrodes to be positioned much closer to the capacitance formation parts, significantly reducing ESR and ESL while maintaining ease of assembly through standardized mount board connections.
Solution Approach 2:
The patent introduces a mount board as an intermediary component between the capacitor elements and the external circuit. The mount board provides a common plane for connecting multiple capacitor elements, enabling short current paths from the capacitance formation parts to the outer electrodes. This intermediary structure resolves the contradiction by facilitating both easy assembly (through standardized connections) and low ESR/ESL (through optimized geometry).
2Ease of manufacture
If traditional stacking methods are used, then capacitor assembly is straightforward, but the ratio of capacitance formation part volume to overall capacitor volume is small, making it difficult to produce thin capacitors
Solution Approach 1:
The patent arranges capacitor elements in a planar configuration rather than stacking them vertically. This allows the capacitance formation parts to be distributed across a larger area close to the mount board, increasing the effective volume ratio of capacitance formation parts while reducing the overall height of the capacitor. The side-by-side arrangement maximizes the use of available space for capacitance formation.
Solution Approach 2:
The patent optimizes the local arrangement of capacitor elements around the mount board to maximize the volume of capacitance formation parts within the available space. By positioning elements strategically and using the mount board as a common reference plane, the design increases the proportion of volume dedicated to capacitance formation without compromising assembly ease.
Data Source
AI summary
A solid electrolytic capacitor comprises a capacitor element including a valve-acting metal substrate including a core part and a porous part disposed on at least one principal surface of the core part, a dielectric layer formed on a surface of the porous part and a solid electrolyte layer is disposed on the dielectric layer. The capacitor element further includes a conductive layer disposed on the solid electrolyte layer. A sealing resin is located on the conductive layer and seals a principal surface of the capacitor element. A cathodic outer electrode is located on the sealing resin and is electrically connected to the conductive layer by a cathodic via electrode which extends through the sealing resin. An anodic outer electrode is electrically connected to the core part.