Ultra Shallow Junction Formation via Solid Phase Diffusion
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Solution Overview
Problem
MOSFET devices face challenges with short channel effects (SCE) such as increased gate to drain overlap capacitance and current leakage due to difficulties in controlling ultra-shallow junction depths and dopant concentration, leading to parasitic resistance and substrate damage during ion implantation and thermal processes.
Innovation Solution
A method involving the formation of ultra-shallow junctions using solid phase diffusion with selective epitaxial growth and offset spacers to control dopant out-diffusion, reducing lateral diffusion and parasitic resistance, and enhancing dopant concentration and interface definition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If junction depth is decreased to reduce short channel effects, then device operating characteristics are improved, but parasitic resistance increases
Solution Approach 1:
The patent applies local quality by creating distinct regions with different dopant concentrations: high dopant concentration in the ultra-shallow junction region to reduce parasitic resistance, and lower concentration in deeper regions. This spatial variation in dopant concentration optimizes both low resistance and short channel effect suppression locally.
Solution Approach 2:
The patent uses preliminary action through selective epitaxial growth to form raised source/drain regions before final dopant activation. This pre-formed structure provides a template that controls subsequent dopant diffusion, ensuring ultra-shallow junction formation while maintaining low parasitic resistance through the raised region geometry.
2Manufacturing precision
If ion implantation energy is reduced to achieve shallower junctions, then junction depth is decreased, but substrate damage increases
Solution Approach 1:
The patent introduces solid phase diffusion as an intermediary process between ion implantation and final junction formation. The dopants are first implanted at higher energy to ensure sufficient substrate penetration, then a solid phase diffusion step with offset spacers acts as a mediator to redistribute the dopants to the desired ultra-shallow depth while repairing implantation damage through the controlled thermal process.
Solution Approach 2:
The patent changes the physical state and temperature parameters during processing. By heating the structure to activate solid phase diffusion, the dopant distribution is thermally controlled rather than solely relying on implantation energy. This parameter change allows shallower effective junctions without the extreme low-energy implantation that causes substrate damage.
3Reliability
If thermal processes are used following ion implantation, then dopant activation is achieved, but lateral diffusion increases
Solution Approach 1:
The patent extracts or removes the harmful lateral diffusion effect by introducing offset spacers that physically block dopant movement laterally. The spacers are selectively removed only from regions where lateral diffusion is desired, thereby taking out the unwanted lateral diffusion from the overall process while preserving necessary dopant activation.
Solution Approach 2:
The offset spacers act as intermediaries that mediate between the thermal activation process and the final dopant distribution. During the thermal activation step, the spacers are present to limit lateral diffusion, then selectively removed to create the final desired profile, thus mediating the conflict between activation and lateral diffusion control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved control over SDE regions, reducing SCE effects, enhancing drive current, and improving device reliability and performance by forming shallow, well-defined junctions with reduced electrical resistance and lateral diffusion.
Implementation Method 1
thermally treating the at least one semiconductor layer to cause out-diffusion of the dopants to form doped regions in the semiconductor substrate
Implementation Method 2
providing raised S/D regions by raising up the S/D contact surface by selective epitaxial silicon growth (SEG) over the S/D contact regions
Data Source
AI summary
An ultra shallow junction (USJ) FET device and method for forming the same with improved control over SDE or LDD doped region interfaces to improve device performance and reliability is provided, the method including providing a semiconductor substrate; forming a gate structure comprising a gate dielectric, an overlying gate electrode, and first offset spacers adjacent either side of the gate electrode; forming at least one doped semiconductor layer comprising dopants over a respective source and drain region adjacent the respective first offset spacers; forming second offset spacers adjacent the respective first offset spacers; and, thermally treating the at least one semiconductor layer to cause out-diffusion of the dopants to form doped regions in the semiconductor substrate.