Solid State Device with Distributed Bit Buckets for SSD Performance
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Solution Overview
Problem
Error detection and correction functionalities in SSDs reduce performance and occupy valuable space, as they require additional computations and data processing, leading to increased data traffic through physical interconnects.
Innovation Solution
A solid state device (SSD) with a controller that includes a processor, memory, and direct memory access (DMA) circuitry, where the DMA circuitry determines whether a requested address is part of a subset of addresses configured as bit buckets, allowing for the provision of pre-determined data without retrieving actual data from memory, thereby reducing unnecessary data traffic and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection and correction functionality is implemented in the SSD controller, then data accuracy is improved, but SSD performance speed deteriorates due to additional computations and processing
Solution Approach 1:
The patent segments the error detection and correction functionality by distributing bit bucket operations across multiple hardware engines within the controller. Each hardware engine has dedicated circuitry for specific error checking tasks, allowing parallel processing that maintains data accuracy while improving overall system throughput and performance speed.
Solution Approach 2:
The patent introduces an intermediary bit bucket mechanism that acts as a buffer between data storage and error detection processes. This intermediary structure allows error checking to be performed on predetermined data patterns without requiring full data retrieval, reducing the computational burden on the controller and improving access speed while maintaining reliability.
2Reliability
If error detection and correction functionality is implemented in the SSD controller, then data accuracy is improved, but valuable memory space is consumed by allocating memory blocks for error detection and correction data
Solution Approach 1:
The patent extracts the error detection and correction data from the main memory blocks and stores them in dedicated bit bucket structures within the hardware engines. This separation allows the controller to maintain error checking capabilities without consuming valuable memory space that would otherwise be available for user data storage.
Solution Approach 2:
The patent uses copying by creating simplified representations of error detection data in the bit bucket structures. Instead of storing complete error correction codes in main memory, the system maintains compact copies of essential error checking information in the hardware engine buffers, reducing memory space requirements while preserving data accuracy.
3Reliability
If error detection and correction operations are performed by the controller, then data accuracy is improved, but data traffic through physical interconnects increases creating processing overhead
Solution Approach 1:
The patent performs preliminary error detection actions by checking data integrity at the hardware engine level before data is fully transferred through the controller's physical interconnects. This preliminary checking prevents unnecessary data traffic by identifying and handling errors locally, reducing the energy consumption associated with transmitting and processing additional verification data through the entire controller.
Data Source
AI summary
Aspects of the disclosure provide a solid state device that includes a non-volatile memory and a controller. The controller includes a processor, a memory, and a direct memory access (DMA) circuitry. The memory comprises a plurality of addresses. The DMA circuitry is configured to receive a first read request for data stored at a first address of the memory; determine whether the first address is an address from the plurality of addresses; when the first address is amongst the plurality of addresses, provide a first response comprising a particular data, without retrieving data stored at the first address; and when the first address is not amongst the plurality of addresses, retrieve the data stored at the first address, and provide a first response comprising the data retrieved from the first address.