Solid State Device Stress Testing via Access Pads
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Solution Overview
Problem
Existing methods for testing solid state devices often require post-manufacture access, which is not feasible for all components, and field plates in devices like GaN devices prevent proper electric field formation, leading to incomplete quality assurance and potential latent defects.
Innovation Solution
Applying voltages to conductive layers during the manufacturing process to stress dielectric layers before additional layers are formed, using patterned conductive layers with access pads to minimize damage and ensure targeted electric field formation, and repeating stress testing throughout the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If post-manufacture testing is performed, then quality assurance is achieved, but access to all components is not feasible
Solution Approach 1:
The patent applies stress testing to dielectric layers during the manufacturing process, before completing device fabrication. By performing the testing action preliminarily on partially-manufactured devices with exposed conductive layers, the patent eliminates the need for post-manufacture access to internal components, resolving the contradiction between achieving quality assurance and accessing all components.
2Ease of manufacture
If field plates are used in GaN devices, then device structure is formed, but proper electric field formation for testing is prevented
Solution Approach 1:
The patent performs stress testing on dielectric layers before field plates are formed in GaN devices. By completing the testing action preliminarily on partially-manufactured devices, the patent avoids the interference that field plates would create, ensuring proper electric field formation for testing while still allowing complete device structure formation later.
3Reliability
If stress testing is performed on completed devices, then quality assurance is achieved, but testing-related damage occurs
Solution Approach 1:
The patent applies stress testing preliminarily during the manufacturing process on partially-manufactured devices, before the complete device structure is formed. This timing reduces testing-related damage because the device is more robust during manufacturing and can better withstand stress testing, while still achieving comprehensive quality assurance of critical components.
4Reliability
If comprehensive stress testing is performed, then all components meet performance parameters, but manufacturing process time increases
Solution Approach 1:
The patent integrates stress testing into the manufacturing process itself, performing testing actions preliminarily on dielectric layers as they are formed, rather than adding separate post-manufacture testing steps. This integration eliminates idle time and ensures continuous productive action, verifying performance parameters without significantly increasing total manufacturing time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for comprehensive stress testing of solid state devices before completion, reducing testing-related damage and ensuring that all components meet performance parameters, thereby improving quality assurance and defect detection.
Implementation Method 1
applying a voltage to the conductive layer using the access pad, the voltage forming an electric field in an area of the first layer beneath the conductive layer
Data Source
AI summary
In some examples, a method for manufacturing a solid state device comprises forming a first layer of the solid state device; forming a conductive layer of the solid state device above the first layer, the conductive layer having an access pad formed on an end of the conductive layer; applying a voltage to the conductive layer using the access pad, the voltage forming an electric field in an area of the first layer beneath the conductive layer; and completing manufacture of the solid state device after applying the voltage.