Solid-State Disconnect Device Using Depletion and Enhancement Mode FETs
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Solution Overview
Problem
Traditional solid-state protection devices require additional power sources and suffer from high conduction resistance, voltage blocking limitations, and difficulty in controlling tripping current due to the use of p-channel FETs, leading to inefficiencies and increased costs.
Innovation Solution
A two-terminal solid-state disconnect device utilizing depletion mode and enhancement mode circuit blocks with a current limiting load, connected in series, which eliminates the need for an additional power source and leverages wide bandgap semiconductor power devices for improved voltage blocking and reduced conduction loss, enabling efficient high-voltage and high-current protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If p-channel high-voltage FETs are used to achieve voltage blocking capability, then the device can block high voltage, but the conduction resistance increases due to low hole mobility
Solution Approach 1:
The patent changes the channel type from p-channel to n-channel FETs, fundamentally altering the charge carrier parameter from holes to electrons. This parameter change enables high voltage blocking capability while maintaining low conduction resistance, as n-channel FETs have superior electron mobility compared to hole mobility in p-channel FETs.
Solution Approach 2:
The patent employs a composite structure combining multiple n-channel FETs with different characteristics. Specifically, it uses a first n-channel FET for voltage blocking and a second n-channel FET for current conduction, creating a composite device that optimizes both voltage blocking capability and conduction performance.
2Strength
If both gate-to-source terminals and gate-to-drain terminals of FETs are designed to have high-voltage blocking capability, then the device achieves symmetric voltage blocking, but this is difficult to achieve because FETs naturally block voltage between drain-to-source and drain-to-gate terminals with low-voltage blocking at gate-to-source terminal
Solution Approach 1:
The patent segments the voltage blocking function across different components. The n-channel FETs provide drain-to-source voltage blocking, while the gate-to-source voltage blocking is achieved through the intrinsic characteristics of the n-channel FET structure combined with the circuit configuration. This segmentation allows achieving symmetric voltage blocking without requiring complex modifications to individual FET terminals.
Solution Approach 2:
The patent introduces a capacitor as an intermediary element connected between the gate and source terminals. This capacitor mediates the voltage blocking requirement by blocking DC voltage while allowing AC signals to pass, thereby achieving the desired voltage blocking capability without compromising the FET's natural electrical characteristics.
3Strength
If a large number of FETs are connected in series to increase voltage blocking capability, then the voltage blocking capability increases, but the conduction loss increases
Solution Approach 1:
The patent uses a composite structure with parallel-connected n-channel FETs instead of series connection. The first and second n-channel FETs are connected in parallel, which reduces the total conduction loss while maintaining the required voltage blocking capability through proper device selection and circuit configuration.
Solution Approach 2:
The patent changes the connection topology from series to parallel configuration of FETs. This parameter change in the circuit architecture allows achieving the desired voltage blocking capability with reduced conduction losses, as parallel connection reduces the total on-resistance compared to series connection.
4Adaptability or versatility
If traditional solid-state protection devices with additional power sources are used, then the device functionality is enhanced, but the device complexity and cost increase
Solution Approach 1:
The patent designs the protection device to be self-powered, eliminating the need for external power sources. The device utilizes the power from the protected circuit itself to operate, with the n-channel FETs and associated components forming a self-sufficient protection system that automatically detects and responds to fault conditions without requiring additional power supply infrastructure.
Solution Approach 2:
The patent extracts and eliminates the additional power source requirement from the protection device architecture. By removing this external dependency, the invention simplifies the overall system while maintaining full protection functionality through the intelligent use of the protected circuit's own power.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides fast tripping speed, low insertion loss, and bidirectional protection, with automatic reset and temperature insensitivity, effectively addressing the limitations of traditional devices while reducing costs and enhancing system reliability.
Implementation Method 1
With the introduction of wide bandgap semiconductor power devices, such as those based on silicon carbide (SiC), gallium nitride (GaN), and diamond, direct serial connectivity of protection devices in the circuit or system to be protected is more feasible at voltages over 10,000 volts, because these wide bandgap switches have a specific ON-state resistance nearly a thousand times lower than silicon components.
Implementation Method 2
The CLL could be a simple resistor or a dynamic load formed by a circuit having a resistance that increases with terminal voltage.
Data Source
AI summary
A solid-state disconnect device capable of isolating and protecting circuits and equipment from overloads and undesired transients is presented. The protection device includes at least one depletion mode circuit block having three terminals (drain, gate, and source), which in its simplest form is implemented by a single n-channel depletion mode field-effect transistor, and two enhancement mode circuit blocks each having three terminals (drain, gate and source), each implemented in simplest form by a single n-channel enhancement mode field-effect transistor. The current conducting path of the first enhancement mode circuit block is connected in series with the current conducting path of the depletion mode circuit block. The drain terminal of the second enhancement mode circuit block is connected through a current limiting load to both the gate terminal of the second enhancement mode circuit block and the drain terminal of the first enhancement mode circuit block. The gate terminal of the first enhancement mode circuit block is connected to the drain terminal of the second enhancement mode circuit block. The source terminals of the two enhancement circuit blocks are both connected to the gate terminal of the depletion mode circuit block. Unidirectional and bidirectional embodiments are disclosed.