Solid-State Imaging Device 6-Pixel 1-Cell Structure
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Solution Overview
Problem
Conventional solid-state imaging devices face challenges in increasing pixel integration density due to the sharing of transistors and wirings, which lead to image deterioration, shading, and reduced effective charge accumulation, particularly with finer cell patterning.
Innovation Solution
A 6-pixel 1-cell structure is implemented with shared output circuits and reduced shallow trench isolation, utilizing ion implantation for element isolation, which reduces the number of transistors and wirings per pixel, thereby minimizing shading and maintaining effective charge accumulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shallow trench isolation is increased to isolate PDs and transistors, then element isolation is improved, but the effective area of PD is reduced and saturation charges are reduced
Solution Approach 1:
The patent merges the isolation function into the STI structure itself by forming the STI region to extend into the PD region, eliminating the need for separate isolation regions around each PD. This integration maintains element isolation while maximizing the effective PD area by removing redundant isolation structures.
Solution Approach 2:
The patent changes the dimensional approach of isolation by extending the STI region vertically into the PD region rather than only horizontally around it. This vertical extension provides effective isolation while preserving horizontal PD area, resolving the contradiction between isolation effectiveness and PD area.
2Device complexity
If the number of wirings is increased to support more transistors per pixel, then transistor functionality is improved, but light collection efficiency is lowered causing shading deterioration
Solution Approach 1:
The patent merges multiple transistor functions into shared circuits that serve multiple PDs. By having transistors and wirings serve multiple pixels rather than being dedicated to single pixels, the wiring density per PD is reduced, improving light collection efficiency while maintaining necessary transistor functionality through sharing.
3Productivity
If cell patterning is made finer to increase pixel density, then integration density is improved, but image deterioration and shading increase
Solution Approach 1:
The patent merges multiple PDs into a shared cell structure where common circuits serve multiple photodiodes. This merging approach allows finer cell patterning to achieve higher integration density while the shared structure reduces the relative impact of isolation and wiring on each individual PD, thereby maintaining image quality despite smaller cell sizes.
4Device complexity
If transistors are shared among multiple PDs to reduce the number of transistors per pixel, then device complexity is reduced, but element isolation regions increase
Solution Approach 1:
The patent merges the isolation function into the shared STI structure that serves multiple PDs and transistors simultaneously. By creating a unified isolation structure rather than separate isolation regions for each component, the total isolation area is reduced while still providing necessary element isolation, thereby allowing transistor sharing without proportionally increasing isolation regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances image quality by reducing white scratches, maintaining saturation charge levels, and improving light collection efficiency, while allowing for miniaturization without significant damage to the semiconductor substrate.
Implementation Method 1
photodiodes (hereinafter referred to as PDs) are provided to accumulate charges generated by photoelectric conversion
Implementation Method 2
an impurity region is prepared around the trench such that a depletion layer from the PDs does not reach a damaged region
Data Source
AI summary
Provided is a solid-state imaging device. Two unit cells are prepared each having three pixels and sharing an output circuit. One of the basic blocks is rotated by 180° such that a reset drain is shared, resulting in a 6-pixel 1-cell, and the cells are disposed in a square lattice pattern or checkerboard pattern. Thus, element isolation regions between the pixels and the output circuit disposed adjacent thereto are minimized, and the number of wirings disposed around the pixels is reduced. As a result, a margin for white scratches and saturation charge amounts may be increased despite the miniaturization of cells.