Solid-State Imaging Device Complementary Signal Transfer
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Solution Overview
Problem
The parasitic capacitance in horizontal signal lines of solid-state imaging devices limits high-speed operation and data transfer, particularly in high-frame-rate applications, due to increased load capacitance and line resistance, which restricts the number of pixels that can be processed efficiently.
Innovation Solution
The implementation of a solid-state imaging device that transfers pixel information as complementary signals, which are then amplified and compared differentially to reproduce the original information, effectively canceling noise and reducing the impact of parasitic capacitance, allowing for higher-speed data transfer with reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If pixel information is transferred through horizontal signal lines, then data transfer is achieved, but parasitic capacitance increases causing signal delay and limiting transfer speed
Solution Approach 1:
The pixel array is divided into multiple blocks, with each block independently transferring pixel information to its corresponding processing unit. This segmentation reduces the capacitance load on each horizontal signal line by limiting the transfer distance and number of pixels per line, thereby improving transfer speed while reducing parasitic capacitance effects.
Solution Approach 2:
The patent introduces a block-based two-dimensional organization (blocks × processing units) in addition to the traditional pixel array structure. This dimensional change allows parallel processing of multiple pixel blocks simultaneously, increasing overall data transfer throughput while keeping individual horizontal signal line loads manageable.
2Measurement precision
If the number of pixels is increased, then image resolution is improved, but the influence of parasitic capacitance and line resistance increases, restricting processing efficiency
Solution Approach 1:
By dividing the large pixel array into smaller blocks, each block can be processed independently by dedicated processing units. This allows the system to handle high-resolution images with many pixels by processing them in manageable chunks, maintaining processing efficiency while supporting increased pixel counts for higher resolution.
Solution Approach 2:
Pixel information is pre-organized into blocks before being transferred to processing units. This preliminary blocking and organization allows for efficient parallel processing, where multiple blocks are prepared and transferred simultaneously, improving overall processing efficiency for high-resolution images.
3Productivity
If high-frame-rate operation is implemented, then video capture speed is improved, but the load capacitance and line resistance increase, limiting the achievable frame rate
Solution Approach 1:
The pixel array is segmented into multiple blocks that can be read out and processed in parallel. This parallel block processing reduces the time required to read out the entire pixel array, enabling high frame rates without requiring excessively fast (and power-consuming) sequential readout of all pixels.
Solution Approach 2:
Instead of reading out all pixels simultaneously at full speed (which would require excessive power), the system reads out pixel blocks in parallel at moderate speeds. The cumulative effect of multiple parallel block transfers achieves the high frame rate goal while keeping individual transfer operations within power consumption limits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-speed data transfer and reduces the influence of noise, improving the overall performance and accuracy of image capture while minimizing the impact of parasitic capacitance, thus supporting increased pixel counts and faster operation.
Implementation Method 1
the parasitic capacitance present in signal lines for horizontal transfer (information transfer paths: in particular, referred to as horizontal signal lines) poses a problem
Implementation Method 2
a differential amplifying unit that receives the signals on the two kinds of complementary signal lines with differential inputs and compares the signals
Data Source
AI summary
A solid-state imaging device includes a pixel unit in which unit pixels are arrayed, a complementary-signal generating unit that generates two kinds of complementary signals having complementarity with each other on the basis of analog pixel signals read out from the respective unit pixels in the pixel unit, two kinds of complementary signal lines on which the two kinds of complementary signals are transmitted, a horizontal scanning unit that transfers each of the two kinds of complementary signals on the complementary signal lines, and a differential amplifying unit that receives the signals on the two kinds of complementary signal lines with differential inputs and compares the signals.