Solid-State Imaging Device 2x4n Pixel Sharing Layout
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
MOS solid-state imaging devices face a challenge in achieving increased sensitivity while miniaturizing pixels, as further miniaturization reduces the aperture area of the light receiving portion, leading to decreased sensitivity.
Innovation Solution
The implementation of a solid-state imaging device with a layout where one sharing unit includes an array of photodiodes arranged 2 pixels by 4xn in horizontal and vertical directions, allowing for reduced pixel transistors per pixel, increased aperture area, and independent readout wirings for each pixel, enabling pixel addition within floating diffusions and reducing column signal processing circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixels are miniaturized to increase resolution, then the number of pixels per unit area increases, but the aperture area of each photodiode decreases leading to reduced sensitivity
Solution Approach 1:
The patent divides the pixel array into sharing units with a specific 2×4×n photodiode arrangement, where photodiodes are segmented into groups that share readout circuitry. This segmentation allows for optimized light collection within each group while maintaining high overall resolution, resolving the contradiction between miniaturization and sensitivity.
Solution Approach 2:
The patent introduces a three-dimensional layout configuration (2 pixels × 4 pixels × n pixels) that adds a depth dimension to the traditional two-dimensional pixel array. This dimensional expansion allows for increased aperture area in the vertical stacking direction while maintaining high horizontal resolution, thereby improving sensitivity without sacrificing resolution.
2Length of moving object
If the number of pixel transistors per pixel is reduced to enable further pixel miniaturization, then pixel area decreases, but the complexity of sharing structures increases
Solution Approach 1:
The patent merges multiple photodiodes (2×4×n arrangement) to share common readout circuitry including floating diffusions and amplifiers. This merging reduces the number of transistors required per pixel while organizing the sharing structure in a systematic 2×4×n pattern that manages complexity through regularity and modularity.
Solution Approach 2:
The shared readout circuitry serves multiple photodiodes simultaneously, making the circuitry universal rather than dedicated to single pixels. The floating diffusion nodes and amplifiers perform multiple functions by serving different photodiodes in the 2×4×n array, reducing overall device complexity while enabling pixel miniaturization.
3Reliability
If aperture area is increased to improve sensitivity, then pixel area increases, but the number of pixels that can be packed in a given area decreases
Solution Approach 1:
The patent resolves this contradiction by utilizing vertical stacking (the n dimension in 2×4×n) to increase aperture area. Photodiodes are arranged in multiple layers along the vertical axis, allowing each photodiode to have a larger effective light-collecting area while maintaining high horizontal pixel density. This three-dimensional arrangement enables both large aperture and high resolution simultaneously.
Solution Approach 2:
The patent segments the pixel array into multiple sharing units with 2×4×n photodiode configurations, where each segment optimizes aperture area locally. By dividing the overall array into manageable sharing units, the system achieves high total resolution through many segments while each segment maintains sufficient aperture area for sensitivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances sensitivity and allows for high-quality electronic apparatus performance even when pixels are miniaturized, by increasing the aperture area of photodiodes and optimizing pixel layout for improved light collection efficiency.
Implementation Method 1
each pixel is composed of a photodiode serving as a photoelectric conversion unit
Data Source
Figure 1
Figure 2
Figure 3A~3C
AI summary
A solid-state imaging device includes a layout in which one sharing unit includes an array of photodiodes of 2 pixels by 4xn pixels (where, n is a positive integer), respectively, in horizontal and vertical directions.