Solid-State Imaging Device With Sub-Chip Opening
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Solution Overview
Problem
In solid-state imaging devices, the lamination of wafers with chips of different planar areas limits the flexibility and efficiency of chip size and layout, leading to reduced yield and performance due to constraints in wafer thinning and stress-induced distortion.
Innovation Solution
A solid-state imaging device configuration that includes a first substrate with a pixel portion, a second substrate with an opening for supporting a sub-chip, and electrical connection through the opening, allowing for greater flexibility in chip size and layout without the need for additional carriers or thinning processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If wafers with chips of different planar areas are laminated together using conventional methods, then chips can be electrically connected through through holes, but the number and layout of chips are limited by the wafer with the largest planar area, reducing the degree of freedom in chip size and layout
Solution Approach 1:
The invention divides the support structure into two separate components: a carrier substrate that provides mechanical support and a separate wafer that contains the chips. This segmentation allows the carrier substrate to be optimized for support functions while the wafer can be optimized for chip integration, enabling greater flexibility in chip layout and size without being constrained by the need for uniform wafer thinning across different chip areas.
Solution Approach 2:
The carrier substrate acts as an intermediary between the chips and the final device structure. It provides a stable platform for mounting chips of varying sizes and shapes, and serves as the interface for electrical connections through conductive bumps or pads, eliminating the need for complex through-hole structures that would be required if chips were directly integrated into a single wafer.
2Adaptability or versatility
If additional carrier wafers are used to support sub-chips, then chip layout flexibility is improved, but the manufacturing process becomes more complex and requires additional thinning processes
Solution Approach 1:
The invention merges the support function and the electrical connection function into a single integrated carrier substrate. This eliminates the need for separate carrier wafers and reduces the number of manufacturing steps, as the carrier substrate can be directly bonded to the chip wafer without requiring additional thinning or alignment processes.
Solution Approach 2:
The carrier substrate is designed to automatically provide both mechanical support and electrical connectivity through its inherent structure. The conductive bumps or pads on the carrier substrate self-align with corresponding contact points on the chip wafer during bonding, eliminating the need for complex alignment and connection processes that would otherwise be required.
3Reliability
If through holes filled with metal material are used to electrically connect chips, then electrical connection is achieved, but the manufacturing process becomes more complex and time-consuming
Solution Approach 1:
The electrical connection structures (conductive bumps or pads) are pre-formed on the carrier substrate before chip mounting. This preliminary preparation allows for rapid chip attachment and electrical connection without requiring time-consuming through-hole drilling, filling, and bonding processes during final assembly.
Solution Approach 2:
The invention replaces the mechanical through-hole connection system with a surface-mounted electrical connection system using conductive bumps or pads. This substitution eliminates the need for complex drilling, filling, and bonding operations, significantly reducing manufacturing time while maintaining reliable electrical connections through direct contact interfaces.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the degree of freedom in chip layout and size, reduces distortion, and simplifies the manufacturing process by eliminating the need for carrier wafers, thereby improving the yield and performance of solid-state imaging devices.
Implementation Method 1
a second substrate which is bonded to a surface of the first substrate opposed to the one principal surface
Data Source
AI summary
Provided is a solid-state imaging device that includes a first substrate that has one principal surface on which a pixel portion in which pixels are arranged is formed, a second substrate which is bonded to a surface of the first substrate opposed to the one principal surface and in which an opening is provided in a partial region in a surface opposed to a bonding surface to the first substrate is provided. The solid-state imaging device further includes at least one sub-chip inside the opening so as not to protrude from the opening and in which a circuit having a predetermined function is formed.