Solid-State Imaging Device Vertical Photodiode Stacking
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Solution Overview
Problem
CMOS image sensors face a trade-off where expanding the photodiode area to improve saturation charge and sensitivity characteristics reduces the transistor area, leading to increased random noise and lower circuit gain, while securing the transistor area lowers the photodiode's performance.
Innovation Solution
The solution involves forming photodiodes and pixel transistors in different regions of a silicon substrate, with an epitaxial layer and transfer transistors that extend from the photodiodes to the epitaxial layer, allowing for a larger photodiode area without compromising the transistor region, and using pinning layers and floating diffusion to enhance sensitivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the photodiode area is expanded to improve saturation charge and sensitivity characteristics, then the amount of saturation charge and sensitivity characteristics are improved, but the transistor area is reduced, causing random noise to worsen and circuit gain to lower
Solution Approach 1:
The patent applies three-dimensional stacking to separate photodiodes and transistors into different vertical layers. The first photodiode is formed in a first region and the second photodiode is formed in a second region above the first region, allowing both photodiodes to have large areas without compromising transistor performance. This vertical arrangement resolves the area trade-off by utilizing the third dimension (height) rather than competing for planar space.
Solution Approach 2:
The patent implements a nested structure where multiple photodiodes are stacked vertically with one above the other. The first photodiode is positioned below the second photodiode, and both are connected to separate transfer transistors. This nesting allows the pixel structure to contain multiple functional elements within a compact footprint, effectively increasing the total photodiode area while maintaining adequate space for transistor operations.
2Reliability
If the area of the transistors is secured, then the random noise and circuit gain are maintained, but the photodiode area is reduced, lowering the amount of saturation charge and sensitivity characteristics
Solution Approach 1:
By transitioning to a three-dimensional stacked architecture, the patent allows transistors to be positioned in the vertical dimension rather than competing for horizontal space with photodiodes. This separation enables both components to maintain their required areas independently, with transistors having adequate area for low noise and high gain while photodiodes have sufficient area for high sensitivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the saturation charge and sensitivity characteristics of the photodiodes while maintaining the transistor area, reducing random noise and enhancing image capture performance.
Implementation Method 1
At least a first photodiode, with the first photodiode being formed in the silicon substrate
Data Source
AI summary
Solid-state imaging devices, methods of producing a solid-state imaging device, and electronic apparatuses are provided. More particularly, a solid-state image device includes a silicon substrate, and at least a first photodiode formed in the silicon substrate. The device also includes an epitaxial layer with a first surface adjacent a surface of the silicon substrate, and a transfer transistor with a gate electrode that extends from the at least a first photodiode to a second surface of the epitaxial layer opposite the first surface. In further embodiments, a solid-state imaging device with a plurality of pixels formed in a second semiconductor substrate wherein the pixels are symmetrical with respect to a center point is provided. A floating diffusion is formed in an epitaxial layer, and a plurality of transfer gate electrodes that are each electrically connected to the floating diffusion by one of the transfer gate electrodes is provided.