Solid State Memory Error Reduction via Adaptive Reference Voltage
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Solution Overview
Problem
Solid state storage devices experience increased error rates over time, which conventional error correction circuitry is unable to fully address, necessitating advanced methods to reduce errors in solid state memory.
Innovation Solution
The method involves programming a multi-bit cell with a first value based on a bit value, reading it using a modified reference value to generate read data, and adjusting the reference value to reduce bit error rates, including calibrating the reference value by comparing error rates from test voltage readings to select an optimal threshold, thereby minimizing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If enhanced error correction circuitry is employed to correct additional errors, then error correction capability is improved, but device complexity increases and not all mis-programming errors can be corrected
Solution Approach 1:
The patent changes the parameter of reference voltage values used during read operations. By dynamically adjusting reference voltage levels based on programmed distribution characteristics, the system achieves improved error correction without adding complex circuitry. The method modifies read operation parameters rather than hardware architecture.
Solution Approach 2:
The patent replaces hardware-based error correction mechanisms with a software/firmware-based approach. Instead of using complex error correction circuitry, the system uses modified read operations with adjusted reference voltages and iterative decoding algorithms to correct errors, substituting mechanical/electrical complexity with computational methods.
2Duration of action of stationary object
If data is stored in solid state memory over time, then storage duration is extended, but bit error rate increases due to data decay
Solution Approach 1:
The patent applies preliminary action by characterizing the programmed distribution of threshold voltage values during programming operations. This characterization data is stored and later used to adjust reference voltage levels during read operations, proactively compensating for data decay before errors occur. The system prepares correction parameters in advance based on programming conditions.
Solution Approach 2:
The patent implements feedback by using read operations to detect errors and then adjusting subsequent read operations with modified reference voltage levels. The system continuously monitors bit error rates and adapts reference voltage characteristics based on observed data decay patterns, creating a closed-loop error correction mechanism.
3Ease of operation
If conventional reference values are used for reading data, then read operation simplicity is maintained, but bit error rate increases over time
Solution Approach 1:
The patent introduces dynamics by making reference voltage levels adaptive rather than fixed. The reference voltage characteristics are dynamically adjusted based on programmed distribution characteristics and observed error patterns. This allows the read operation to adapt to changing memory conditions while maintaining operational simplicity through automated adjustments.
Data Source
AI summary
Systems and method relating generally to solid state memory, and more particularly to systems and methods for reducing errors in a solid state memory.