Solid-State Memory Auto-Correction via Dual Parity
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Solution Overview
Problem
Current solid-state storage systems face challenges with data corruption and error correction, particularly in flash memory, where wear out and external influences lead to increased latency, longer write and erase operations, and the inability to identify and correct errors in multiple faulty disk drives, resulting in significant IO delays and data loss.
Innovation Solution
A method for auto-correction of errors in an array of solid-state storage devices using a dual parity generation engine that identifies and corrects errors in real-time by transferring data through channel memories and a stage buffer, allowing valid data to be provided to a processor even if one storage channel fails, thereby maintaining high performance and fault tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction methods are used in solid-state storage systems, then data integrity can be maintained, but the system experiences increased latency, longer write and erase operations, and significant IO delays when errors occur
Solution Approach 1:
The patent pre-calculates and stores parity information for data stripes across multiple solid-state storage devices during the write operation. This preliminary preparation allows the system to immediately reconstruct lost data upon error detection without performing time-consuming calculations during read operations, thereby reducing latency and IO delays while maintaining data integrity
Solution Approach 2:
The patent introduces a parity generation engine and control logic that acts as an intermediary between the storage devices and the processor. This intermediary pre-processes data by generating and storing parity information, enabling rapid error correction through simple lookup and reconstruction operations rather than complex real-time calculations, thus reducing the time penalty associated with error correction
2Reliability
If the system retreats entire blocks when errors are detected, then data integrity is protected, but storage capacity is reduced and performance deteriorates due to loss of usable space
Solution Approach 1:
The patent applies error correction at the granular level of individual data words or small groups of words within a block, rather than treating the entire block as a single unit. By using dual parity generation engines to identify and correct errors locally, the system can salvage and continue to use the majority of the block's storage capacity, significantly improving storage utilization while maintaining data integrity for the corrected portions
Solution Approach 2:
The patent recovers usable data from blocks that would traditionally be retired by using dual parity generation engines to identify and correct errors in specific data words. Instead of discarding the entire block when any error is detected, the system recovers and continues to use the error-free portions of the block, thereby maintaining high storage capacity utilization while ensuring data integrity through selective error correction
3Productivity
If dual parity generation engines are implemented to correct errors in individual data words, then storage capacity utilization improves, but device complexity increases
Solution Approach 1:
The patent divides the parity generation function into separate, dedicated parity generation engines that operate independently on different data stripes. This segmentation allows each engine to be relatively simple in design while collectively providing comprehensive error correction coverage across the entire storage array, managing device complexity through functional decomposition
Solution Approach 2:
The parity generation engines are designed to perform multiple functions: generating parity information during writes, detecting errors during reads, and reconstructing lost data. This multi-functionality reduces the need for separate dedicated components for each operation, thereby managing device complexity while enabling sophisticated error correction that improves storage capacity utilization
Data Source
AI summary
A method for auto-correction of errors in an array of solid-state storage devices having a plurality of storage channels dedicated to storing parity data to provide fault tolerance for a loss of at least two of the plurality of storage channels. A read operation from the storage channels transfers data to a plurality of channel memories. The data in the channel memories is checked to confirm the data is valid. Responsive to detection of invalid data, the data may be tested to identify the storage channel in error, including sequentially excluding data read form a different one of the plurality of channel memories from a parity check and determining the validity of data from remaining channel memories. If valid data is obtained, the storage channel from which the data was excluded is identified as the storage channel in error.