Solid-State Power Storage Chip Layout Without External Battery
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Solution Overview
Problem
Integrated chips with external batteries face challenges due to the large volume and cost of batteries, as well as the reliability issues associated with external connectors.
Innovation Solution
Incorporating a solid-state power storage device within the integrated chip, comprising a first metal layer, an ionic crystal layer, a metal oxide layer, and a hydrous metal oxide layer, which allows for power storage and delivery without an external battery, reducing volume and cost, and eliminating the need for a connector.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an external battery is used to power the integrated chip, then the chip can operate, but the device volume increases and reliability decreases due to connector issues
Solution Approach 1:
The patent merges the power storage function directly into the integrated chip by incorporating a solid-state power storage device within the chip structure. This eliminates the need for external batteries and connectors, thereby improving reliability while reducing device volume. The solid-state power storage device is formed using the same semiconductor manufacturing processes as the chip itself, creating an integrated unit that combines computing and power storage functions.
Solution Approach 2:
The solid-state power storage device is nested within the integrated chip structure, with the battery layers embedded between the transistor layers. This nested configuration allows the power storage component to occupy space within the existing chip architecture rather than requiring external volume, thus reducing overall device size while maintaining functionality.
2Ease of manufacture
If an external battery is used, then power can be supplied, but manufacturing cost increases
Solution Approach 1:
By combining the power storage device with the integrated chip into a single manufactured unit, the patent eliminates the need for separate battery assembly and connector installation processes. This merging reduces manufacturing complexity and cost while simultaneously improving reliability by removing failure points associated with external connectors and separate battery components.
3Volume of moving object
If device size is reduced, then portability improves, but integrating power storage becomes difficult
Solution Approach 1:
The patent solves the space constraint by nesting the solid-state power storage device within the integrated chip structure itself. The battery layers are positioned between transistor layers and share the same vertical space, allowing the power storage function to be embedded without increasing external device volume. This nested approach maintains portability while enabling integration.
Solution Approach 2:
The patent uses solid-state materials with different physical and chemical properties than traditional liquid electrolytes, enabling a compact, stable power storage device that can be integrated at the chip scale. The solid-state nature allows for thinner layers and more efficient space utilization within the chip structure, reducing overall device volume while managing integration complexity through material property optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables a more compact, cost-effective, and reliable integrated chip by providing power internally, suitable for devices like wearables and RFID, with improved reliability by eliminating connector failures.
Implementation Method 1
An ionic crystal layer is between the first metal layer and the second metal layer
Implementation Method 2
A metal oxide layer is between the first metal layer and the second metal layer. A hydrous metal oxide layer is between the ionic crystal layer and the metal oxide layer
Data Source
AI summary
The present disclosure relates to an integrated chip including a first metal layer over a substrate. A second metal layer is over the first metal layer. An ionic crystal layer is between the first metal layer and the second metal layer. A metal oxide layer is between the first metal layer and the second metal layer. The first metal layer, the second metal layer, the ionic crystal layer, and the metal oxide layer are over a transistor device that is arranged along the substrate.