Solid-State Switch Assembly with Integrated Gate Driver
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing gate driver circuits for inverter applications are bulky, consume high power, and are not suited for solid-state switches, particularly in high-voltage DC electrical systems, as they cannot absorb high energy during turn-off under shorted or overload conditions with significant inductance, necessitating a compact, low-power consumption, and reliable gate driver and protection circuit for solid-state switches.
Innovation Solution
An electronic solid-state switch assembly with a base plate and electrically insulating layer, featuring multiple power traces with power semiconductor devices and signal conductors, designed to manage high-voltage and current efficiently, including current limiting and fast fault interruptability, while being lightweight, scalable, and thermally managed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing gate driver circuits are used for solid-state switches, then the switching function can be achieved, but the device becomes bulky and consumes high power
Solution Approach 1:
The gate driver circuit is integrated directly into the solid-state switch device, merging the driver and switch into a single compact unit. This eliminates separate bulky driver components while maintaining the switching function through direct coupling of the gate driver transistors with the power switch elements.
Solution Approach 2:
The integrated circuit performs multiple functions including gate driving, protection, and control within a single device structure. The same semiconductor substrate hosts both the power switching elements and the gate driver circuitry, allowing one device to fulfill roles that previously required separate components.
2Reliability
If existing gate driver circuits are used for solid-state switches, then the switching function can be achieved, but the power consumption becomes high
Solution Approach 1:
The gate driver is merged with the power switch on the same substrate, enabling direct signal coupling with minimal intermediate stages. This integration reduces the number of external connections and intermediate amplification stages that would otherwise consume power, while the shared substrate allows for optimized signal paths.
3Power
If solid-state switches are designed for high current capacity, then the power handling capability is improved, but the device complexity increases
Solution Approach 1:
The high current capacity is achieved by segmenting the device into multiple parallel current paths, each handled by individual power semiconductor elements. These segmented elements are arranged in parallel on the substrate, allowing the device to handle high total current while each individual element maintains a simpler, more manageable structure.
Solution Approach 2:
The device layout transitions from a single-dimensional linear arrangement to a two-dimensional planar configuration on the substrate. Power elements and interconnections are arranged in a distributed pattern across the substrate surface, enabling high current capacity through parallel paths without increasing the vertical complexity of individual components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables continuous operation with a voltage drop of less than one volt, fast switching speeds, and fault tolerance, achieving efficient power management and reliability in high-voltage battery systems for electrified powertrains.
Implementation Method 1
an electrically insulating layer affixed to the base plate
Implementation Method 2
a heat sink thermally connected to the base plate
Data Source
AI summary
A solid-state switch assembly includes a base plate and an electrically insulating layer affixed to the base plate. First, second, third, and fourth power traces are affixed to the electrically insulating layer. First semiconductor devices are arranged on the first power trace to control power flow between the first power trace and the second power trace, second semiconductor devices are arranged on the second power trace to control power flow between the second power trace and the third power trace, and third semiconductor devices are arranged on the third power trace to control power flow between the third and fourth power traces. A first signal conductor communicates with the first semiconductor devices. A second signal conductor communicates with the second semiconductor devices. A third signal conductor communicates with the third semiconductor devices.