Solid State Storage Wear Leveling via Selective Block Replacement
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Solution Overview
Problem
As solid-state storage systems, particularly SSDs, face challenges in wear leveling due to uneven data programming, leading to premature wear of specific memory cells, which limits system performance and requires significant RAM buffer size to manage erase counts across all blocks, constrained by cost and chip area.
Innovation Solution
A solid-state storage system and method that uses a buffer unit to store mapping pages with erase counts and a memory controller to set reference values for searching and replacing worn blocks, reducing the need to load all erase counts into the buffer by sampling and varying the searching conditions based on erase count and access count, allowing efficient wear leveling without increasing buffer size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all erase counts of blocks are loaded into the RAM buffer to perform wear leveling, then the wear leveling process can be executed accurately, but the RAM buffer size must be increased which raises cost and chip area
Solution Approach 1:
The patent extracts only the necessary information (erase counts of blocks that need wear leveling) from the complete set of all block erase counts. Instead of loading all erase counts into the RAM buffer, the system selectively extracts and loads only the relevant block information, thereby reducing the buffer size requirement while maintaining wear leveling functionality
Solution Approach 2:
The patent applies partial action by performing wear leveling on a subset of blocks rather than all blocks simultaneously. The memory controller identifies specific blocks that require wear leveling based on erase count thresholds and processes only those blocks, avoiding the need to load and process the entire block set in the limited RAM buffer
2Adaptability or versatility
If the RAM buffer size is increased to store erase counts of all blocks, then wear leveling can be performed on larger capacity SSDs, but the cost and chip area increase
Solution Approach 1:
The patent segments the wear leveling process into multiple phases or batches. Instead of processing all blocks at once requiring large buffer memory, the system divides the block set into smaller segments that can be processed sequentially within the constraints of the limited RAM buffer size, enabling support for larger SSD capacities without proportionally increasing buffer memory
Solution Approach 2:
The system performs partial wear leveling by selecting and processing only the most critical blocks (those with extreme erase counts) in each iteration. This partial action approach allows the system to provide wear leveling functionality for large-capacity SSDs using a relatively small RAM buffer, as not all blocks require simultaneous processing
3Duration of action of stationary object
If wear leveling is performed frequently to prevent memory cell wear, then the lifespan of memory cells is extended, but the execution time and system performance are reduced
Solution Approach 1:
The patent dynamically changes the wear leveling execution parameters, specifically the threshold for triggering wear leveling and the number of blocks processed per iteration. By adjusting these parameters based on system conditions, the system can extend memory cell lifespan through wear leveling while minimizing the execution time and performance impact by not always processing the maximum number of blocks
Data Source
AI summary
Solid-state storage systems and methods are provided for controlling a wear leveling process for uniform use of the memory cells that replaces worn memory blocks with less frequently used memory blocks. The wear leveling process is performed by changing the physical locations of the storage cells within each memory zone or plane. Reference values of target memory block erase counts and worn memory block erase counts are used for searching target memory blocks to be used as replacements.