Silicon-on-Nothing Structure with Auxiliary Base Layer
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in reducing the short channel effect and improving device performance, particularly in the Silicon-on-Nothing (SON) device structure, due to complex process steps and high costs associated with existing techniques such as epitaxial SiGe sacrifice layers and ion implantation, which are difficult to scale for large-scale integrated circuits.
Innovation Solution
A semiconductor structure and method that incorporates a substrate with a semiconductor base suspended over a cavity, a gate stack, sidewall spacer, and source/drain regions, along with a semiconductor auxiliary base layer with higher doping concentration, simplifying the process and reducing costs by using conventional etching techniques to form a SON device on a common wafer, thereby suppressing the short channel effect and enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If epitaxial SiGe sacrifice layer technique is used to prepare cavity layer, then SON device structure can be formed, but process steps increase and manufacturing complexity increases
Solution Approach 1:
The patent extracts and removes the complex epitaxial SiGe sacrifice layer preparation steps, replacing them with a simplified approach using conventional etching techniques to form the cavity layer directly, thereby reducing process complexity while maintaining the SON device structure quality
Solution Approach 2:
Instead of building the cavity layer through complex epitaxial growth of SiGe and subsequent removal, the patent inverts the approach by directly forming the cavity using conventional etching techniques on the substrate, simplifying the manufacturing process
2Reliability
If ion implantation is used to form super steep retrograde well, then short channel effect is suppressed, but manufacturing difficulty increases for very large scale integrated circuits
Solution Approach 1:
The patent changes the doping concentration parameter by introducing a semiconductor auxiliary base layer with higher doping concentration than the semiconductor base, forming a super steep retrograde well that suppresses the short channel effect while being compatible with conventional manufacturing processes
Solution Approach 2:
The patent uses a disposable semiconductor auxiliary base layer that is heavily doped and then removed or integrated into the final structure, achieving the desired doping profile without the complexity of ion implantation
3Productivity
If feature size is reduced to nanometer scale, then integration level increases, but short channel effect becomes dominant and degrades device performance
Solution Approach 1:
The patent applies local quality by creating a non-uniform doping profile with a heavily doped semiconductor auxiliary base layer adjacent to the channel region, while maintaining low doping concentration in the channel itself, thereby suppressing short channel effects locally without compromising overall device performance
Solution Approach 2:
The patent addresses short channel effects by introducing a vertical dimension solution through the semiconductor auxiliary base layer structure, creating a super steep retrograde well that confines carriers vertically and reduces the impact of short channel effects in scaled devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution simplifies the manufacturing process, reduces costs, and effectively alleviates the short channel effect, improving semiconductor device performance by forming a super steep retrograde well in the SON device structure, making it suitable for large-scale integrated circuits.
Implementation Method 1
the dielectric constant of the cavity structure is significantly reduced, thereby greatly reducing the influence from the two-dimensional electric field effect of a buried oxide layer and thus the DIBL effect
Implementation Method 2
the semiconductor auxiliary base layer with higher doping concentration... forming a super steep retrograde well in the SON device structure, making it suitable for large-scale integrated circuits
Data Source
AI summary
The present invention provides a semiconductor structure, which comprises: a substrate, a semiconductor base, a semiconductor auxiliary base layer, a cavity, a gate stack, a sidewall spacer, and a source/drain region, wherein the gate stack is located on the semiconductor base; the sidewall spacer is located on the sidewalls of the gate stack; the source/drain region is embedded in the semiconductor base and is located on both sides of the gate stack; the cavity is embedded in the substrate; the semiconductor base is suspended above the cavity, the thickness of the middle portion of the semiconductor base is greater than the thickness of the two end portions of the semiconductor base in the direction of the length of the gate, and the two end portions of the semiconductor base are connected to the substrate in the direction of the width of the gate; and the semiconductor auxiliary base layer is located on the sidewall of the semiconductor base and has an opposite doping type to that of the source/drain region, and the doping concentration of the semiconductor auxiliary base layer is higher than that of the semiconductor base. Correspondingly, the present invention also provides a method for manufacturing a semiconductor structure. According to the present invention, the short channel effect can be suppressed, and the device performance can be improved, thereby reducing the cost and simplifying the process.