Silicon On Nothing Structure With Cavity And Contact Layer
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Solution Overview
Problem
Current manufacturing processes for Silicon on Nothing (SON) devices face challenges in reducing contact resistance at source/drain regions, increasing complexity and cost, and require ultra-shallow junction depth, which complicates the downscaling of feature sizes in semiconductor devices.
Innovation Solution
A semiconductor structure and method that includes a substrate with a cavity, a gate stack, sidewall spacers, source/drain regions, and a contact layer, where the contact layer is made of TiSi2, CoSi2, NiSi, or PtSi2, and formed using a simplified process involving wet etching to create a cavity and reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If epitaxial SiGe sacrificial layer process is used to manufacture SON device, then cavity structure is achieved, but manufacturing process complexity increases
Solution Approach 1:
The patent extracts and removes the complex epitaxial SiGe sacrificial layer process, replacing it with a simpler cavity formation method using conventional bulk silicon wafers. The cavity is formed directly through selective removal of sacrificial oxide layers, eliminating the need for complex epitaxial growth and Ge segregation processes while achieving the same SON device structure.
Solution Approach 2:
Instead of forming the cavity through complex epitaxial growth of SiGe layers and subsequent Ge segregation, the patent inverts the approach by forming sacrificial oxide layers first, then selectively removing them to create the cavity. This reverse sequence simplifies the manufacturing process while achieving identical structural results.
2Manufacturing precision
If ion implantation process is used for ultra-shallow junction depth, then device downscaling is enabled, but manufacturing complexity increases
Solution Approach 1:
The patent replaces complex, expensive ion implantation processes with simpler, more cost-effective conventional doping methods. By using disposable sacrificial oxide layers that are selectively removed, the process achieves ultra-shallow junction depths without requiring sophisticated ion implantation equipment and process control.
Solution Approach 2:
The patent changes the fundamental parameters of the doping process by transitioning from ion implantation to alternative doping methods such as diffusion or in-situ doping during selective epitaxial growth. This parameter change enables achievement of ultra-shallow junction depths through different physical mechanisms that are simpler to control and implement.
3Reliability
If contact layer area is increased to reduce contact resistance, then source/drain region performance improves, but device area increases
Solution Approach 1:
The patent applies local quality by creating regions of different properties within the contact structure. Specifically, it forms localized contact holes through the sacrificial oxide layers that expose the underlying silicon, allowing direct metal contact to source/drain regions. This localized approach reduces contact resistance at critical points without requiring extensive contact layer area expansion.
Solution Approach 2:
The patent introduces sacrificial oxide layers as intermediary structures that facilitate precise contact formation. These oxide layers act as mediators that are selectively removed to create contact windows, enabling direct metal-to-silicon contact at source/drain regions without requiring large contact layer areas. The intermediary oxide layer provides a template for precise contact positioning and area control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method simplifies the manufacturing process, lowers costs, and improves device performance by reducing contact resistance at source/drain regions, enabling efficient production of SON devices on common bulk wafers.
Implementation Method 1
forming recesses in the substrates on both sides of the gate stack; and wet-etching the recesses on both sides of the gate stack to form a cavity
Data Source
AI summary
The present invention provides a semiconductor structure, which comprises a substrate, a semiconductor base, a cavity, a gate stack, sidewall spacers, source/drain regions and a contact layer; wherein, the gate stack is located on the semiconductor base, the sidewall spacers are located on sidewalls of the gate stack, the source/drain regions are embedded within the semiconductor base and located on both sides of the gate stack, the cavity is embedded within the substrate, and the semiconductor base is suspended over the cavity, the thickness in the middle portion of the semiconductor base is greater than the thicknesses at both ends of the semiconductor base in a direction along the gate length, and both ends of the semiconductor base are connected with the substrate in a direction along the gate width; the contact layer covers exposed surfaces of the source/drain regions. Accordingly, the present invention further provides a method for manufacturing a semiconductor structure, which is favorable for reducing the contact resistance at the source/drain regions, enhancing the device performance, lowering the cost and simplifying the manufacturing process.