Silicon-On-Nothing MOSFET Air-Gap Junction Control

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Solution Overview

Problem

The reduction of junction depths in Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) is challenging due to the diffusion of implanted impurities, which degrades carrier mobility and increases leakage currents, especially in smaller devices where shallower junctions are required for Short Channel Effect control.

Innovation Solution

The implementation of Silicon-On-Nothing (SON) MOSFETs with air-gaps under channel regions, where epitaxy regions are formed and selectively etched to create an air gap, reducing the junction depth and improving Short Channel Effect control while maintaining carrier mobility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If junction depth is reduced for Short Channel Effect control in smaller MOSFETs, then SCE control is improved, but carrier mobility is degraded and leakage currents increase due to diffusion of implanted impurities

Engineering Contradiction:
ImproveShort Channel Effect controlVSAvoidleakage currents
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent extracts the problematic substrate material directly beneath the channel region by forming air gaps, removing the source of impurity diffusion that causes leakage currents while preserving the necessary junction structures for SCE control

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The substrate is segmented into regions with air gaps created beneath the channel, separating the channel region from the substrate to prevent impurity diffusion while maintaining other substrate functions in non-air-gap areas

Inventive Principle:
Principle #1Segmentation

2Reliability

If pocket implantation is increased for better SCE control and DIBL reduction, then Short Channel Effect control is improved, but carrier mobility in the channel region is degraded

Engineering Contradiction:
ImproveShort Channel Effect controlVSAvoidcarrier mobility degradation
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

By removing the substrate material beneath the channel to create air gaps, the patent eliminates the diffusion path for implanted impurities, allowing pocket implantation to provide SCE control without the harmful side effect of mobility degradation through substrate diffusion

Inventive Principle:
Principle #2Taking out (Extraction)

3Productivity

If device size is reduced for scaling, then integration density is improved, but junction depth control becomes more difficult due to increased sensitivity to impurity diffusion

Engineering Contradiction:
Improveintegration densityVSAvoidjunction depth control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent removes substrate material to create air gaps that act as diffusion barriers, enabling precise junction depth control in scaled devices by physically blocking impurity diffusion paths that would otherwise be problematic in smaller geometries

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

SON MOSFETs effectively reduce leakage currents and improve Short Channel Effect control by creating air-gaps under the channel region, enhancing device performance without degrading carrier mobility.

Implementation Method 1

due to the diffusion of the implanted impurities

Methodology Applied
Scientific EffectDiffusion: Diffusion

Implementation Method 2

SON MOSFETs have air-gaps under channel regions. With the air-gaps, the SCE of the SON MOSFETs is improved, and leakage currents can be reduced

Methodology Applied
Scientific EffectElectrical insulation: Dielectric

Data Source

PatentUS10699941B2MOSFETs with channels on nothing and methods for forming the same
Publication Date: 2020.06.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10699941B2 patent drawing
  • US10699941B2 patent drawing
  • US10699941B2 patent drawing

AI summary

A method includes performing an epitaxy to grow a semiconductor layer, which includes a top portion over a semiconductor region. The semiconductor region is between two insulation regions that are in a substrate. The method further includes recessing the insulation regions to expose portions of sidewalls of the semiconductor region, and etching a portion of the semiconductor region, wherein the etched portion of the semiconductor region is under and contacting a bottom surface of the semiconductor layer, wherein the semiconductor layer is spaced apart from an underlying region by an air gap. A gate dielectric and a gate electrode are formed over the semiconductor layer.