Silicon-on-nothing Transistor with Epitaxial SiGe Channel
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Solution Overview
Problem
The integration of conventional bulk transistors and silicon-on-nothing (SON) devices on a single substrate is challenging due to differences in electrical properties and parasitic effects, requiring a method to combine their benefits while controlling parasitic phenomena and achieving higher density and faster circuit performance.
Innovation Solution
A method for forming transistors on a silicon substrate involving the creation of a gate stack structure on an epitaxial silicon region, encapsulating it with sacrificial spacers, and growing raised epitaxial source and drain regions, which includes selective epitaxial growth of silicon germanium to improve charge mobility and voltage threshold tuning, while using a thin insulating layer to isolate the channel from the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bulk transistor technology is used, then manufacturing simplicity is maintained, but parasitic effects increase and device performance deteriorates
Solution Approach 1:
The invention divides the substrate into two distinct regions: a bulk substrate region for bulk transistors and a separate SON region with a thin insulating layer for SON transistors. This segmentation allows each transistor type to operate in its optimal electrical environment, reducing parasitic effects in SON devices while maintaining manufacturing simplicity through shared substrate infrastructure.
Solution Approach 2:
The patent applies different structural configurations to different regions of the substrate. The SON region features a thin insulating layer (5-20 nm) between the semiconductor layer and substrate, creating locally optimized electrical properties for reduced parasitic effects, while the bulk region maintains direct substrate contact for conventional device performance.
2Speed
If SON technology is used, then parasitic effects are reduced and switching speed improves, but manufacturing complexity increases
Solution Approach 1:
The substrate serves multiple functions: it provides mechanical support for the entire device, electrical isolation for SON regions through the thin insulating layer, and a common platform for both bulk and SON transistor fabrication. This multi-functionality reduces manufacturing complexity by eliminating the need for separate substrates or complex integration processes.
Solution Approach 2:
The thin insulating layer is formed on the substrate before depositing the semiconductor layers for SON transistors. This preliminary action ensures that parasitic effects are minimized from the outset during SON device operation, while the same substrate can subsequently be used for bulk transistor fabrication without additional complexity.
3Productivity
If feature sizes are reduced for higher density, then circuit performance improves, but manufacturing precision requirements increase
Solution Approach 1:
The invention changes the electrical parameter of the substrate- semiconductor interface by introducing a thin insulating layer with specific thickness (5-20 nm) and material properties. This parameter change reduces parasitic capacitance and enables higher circuit density without proportionally increasing manufacturing precision requirements, as the electrical performance is optimized through material selection rather than dimensional control alone.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the integration of both bulk and SON device types on a single substrate, enhancing mobility and voltage control, reducing parasitic effects, and achieving higher density and faster switching speeds with lower power consumption.
Implementation Method 1
selective epitaxial growth of silicon germanium to improve charge mobility
Implementation Method 2
a thin insulating layer to isolate the channel from the substrate
Data Source
AI summary
An improved transistor with channel epitaxial silicon and methods for fabrication thereof. In one aspect, a method for fabricating a transistor includes: forming a gate stack structure on an epitaxial silicon region, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; encapsulating the epitaxial silicon region under the gate stack structure with sacrificial spacers formed on both sides of the gate stack structure and the epitaxial silicon region; forming a channel of the transistor having a width dimension that approximates that of the epitaxial silicon region and the gate stack structure, the epitaxial silicon region and the gate stack structure formed on the channel of the transistor; removing the sacrificial spacers; and growing a raised epitaxial source and drain from the silicon substrate, with portions of the raised epitaxial source and drain in contact with the epitaxial silicon region.