Scale-Out NUMA Remote Memory Controller Latency

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Solution Overview

Problem

Current datacenter architectures face significant latency challenges due to high network communication delays, especially when accessing remote memory, which exceeds local DRAM access latency by a factor of 1000, limiting the performance of large-scale data processing and analytics applications.

Innovation Solution

The implementation of a remote memory controller (RMC) that interfaces directly with an on-die network interface, enabling stateless request/reply exchanges and minimizing kernel, network stack, and I/O bus overheads, allowing for low-latency remote memory access within a small factor of local DRAM access through a lean memory fabric and RDMA-like programming model.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If data is distributed across multiple servers in a datacenter, then storage capacity and memory size can be scaled to petabyte range, but node-to-node communication latency increases to over 100 microseconds

Engineering Contradiction:
Improvememory capacityVSAvoidcommunication latency
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent introduces a remote memory controller (RMC) as an intermediary component that sits between the network interface and remote memory. The RMC receives memory access requests from the local processor, translates them into appropriate network protocols, and manages the actual memory access on remote nodes. This intermediary abstraction layer hides the complexity of distributed memory access and presents a unified memory interface to applications, thereby reducing the effective latency experienced by applications while maintaining scaled memory capacity across multiple servers.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of time

If remote direct access memory (RDMA) is used to reduce end-to-end latency, then remote memory read latency can be reduced to 1.19 microseconds, but it still represents a 10x latency increase over local DRAM

Engineering Contradiction:
Improveremote memory access latencyVSAvoidnetwork processing complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent merges the remote memory controller functionality directly with the network interface card (NIC) by integrating the RMC into the network adapter. This integration allows the network interface to directly initiate and manage memory access operations on remote nodes without requiring separate control logic or additional processing steps. By combining these functions, the system achieves lower latency (closer to local DRAM speeds) while reducing the overall device complexity and overhead associated with managing distributed memory access.

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If deep network stacks and complex network interface cards are used, then networking functionality and protocol support are enhanced, but communication latency increases significantly

Engineering Contradiction:
Improvenetworking capabilityVSAvoidend-to-end latency
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent extracts the essential memory access control functionality from the complex network stack and places it directly in the remote memory controller integrated with the network interface. By taking out only the critical path functions needed for memory access (translation, protocol encapsulation, and direct memory initiation) and removing unnecessary networking layers and processing steps, the system achieves low-latency memory access while maintaining adequate networking capability for the specific use case of distributed memory access.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS9734063B2Scale-out non-uniform memory access
Publication Date: 2017.08.15 ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
  • US9734063B2 patent drawing
  • US9734063B2 patent drawing
  • US9734063B2 patent drawing

AI summary

A computing system that uses a Scale-Out NUMA (“soNUMA”) architecture, programming model, and/or communication protocol provides for low-latency, distributed in-memory processing. Using soNUMA, a programming model is layered directly on top of a NUMA memory fabric via a stateless messaging protocol. To facilitate interactions between the application, OS, and the fabric, soNUMA uses a remote memory controller—an architecturally-exposed hardware block integrated into the node's local coherence hierarchy.