SONET Clock Distribution Mechanism for Circuit Emulation
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Solution Overview
Problem
Current circuit emulation methods require significant resources and network engineering to recover clocks for each TDM port independently, making it unfeasible to support multiple channels efficiently, especially when every port needs independent clock recovery.
Innovation Solution
Implementing a synchronous optical networking (SONET) system that recovers a single clock source and distributes it to all ports, using FPGA registers and software to normalize the frequency and maintain low jitter and wander, allowing multiple TDM streams to share the same clock source.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each TDM port recovers its own clock independently, then timing accuracy for each port is maintained, but resource consumption and device complexity increase significantly
Solution Approach 1:
The patent merges multiple independent clock recovery functions into a single shared clock recovery mechanism. Instead of each TDM port having its own clock recovery resources, the system recovers a single clock from the Ethernet stream and distributes it to multiple TDM ports, significantly reducing FPGA resources and device complexity while maintaining timing accuracy.
Solution Approach 2:
The recovered clock serves multiple functions simultaneously - it is used to time multiple TDM ports and serves as a source clock for the entire system. This universal clock source replaces numerous dedicated clock recovery units, achieving resource efficiency without sacrificing timing performance.
2Adaptability or versatility
If multiple clock sources are used for multiple channels, then timing independence is maintained, but network resources and power consumption increase
Solution Approach 1:
The system combines multiple clock sources into a single shared clock resource. By recovering one clock from the Ethernet stream and distributing it to multiple TDM ports across different channels, the system maintains channel independence while dramatically reducing power consumption compared to independent clock recovery for each channel.
3Measurement precision
If independent clock recovery is implemented for each port, then timing precision is maintained, but network engineering complexity increases
Solution Approach 1:
The patent extracts the clock recovery function from each individual TDM port and consolidates it at the system level. This extraction simplifies network engineering by reducing the number of clock recovery operations from multiple ports to a single centralized recovery process, while timing precision is maintained through proper clock distribution to all ports.
Data Source
AI summary
A clock distribution mechanism for circuit emulation applications, and related method, including one or more of the following: a plurality of digitally controlled oscillators, each of the plurality of digitally controlled oscillators receiving one or more Ethernet packets and generating a recovered clock from the one or more Ethernet packets; a multiplexer for receiving the recovered clocks generated by the plurality of digitally controlled oscillators, selecting a one of the recovered clocks generated by the plurality of digitally controlled oscillators, and outputting the selected one of the recovered clocks; a normalizer that receives a frequency of the selected one of the recovered clocks and generates a normalized frequency output based on the received frequency of the selected one of the recovered clocks and outputs the normalized frequency output; a clock source selector for receiving a plurality of input clock sources, one of the input clock sources being the normalized frequency output of the normalizer, the clock source selector selecting the normalized frequency output from among the plurality of input clock sources and transmitting the selected normalized frequency to a node; and one or more nodes for receiving the selected normalized frequency.